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SN65LVDS9638DGK
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Texas Instruments LVDS ICs, VSSOP-8-0.65mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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SN65LVDS9638DGK
Texas Instruments · LVDS ICs · VSSOP-8-0.65mm
SN65LVDS9638DGK from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supply voltage with recommended operating range of 3 V to 3.6 V (3.3 V nominal). |
| 2 | 1A | input | LVTTL input signal with VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 3 | 2A | input | LVTTL input signal with VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | 2Z | output | Differential (LVDS) inverting output. |
| 6 | 2Y | output | Differential (LVDS) non-inverting output. |
| 7 | 1Z | output | Differential (LVDS) inverting output. |
| 8 | 1Y | output | Differential (LVDS) non-inverting output. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8-0.65mm |
| Category | Interface |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 3 | 3.3 | 3.6 | V | 7 | |
| High-level input voltage | VIH | 2 | V | 7 | |||
| Low-level input voltage | VIL | 0.8 | V | 7 | |||
| Operating free-air temperature | TA | -40 | 85 | °C | SN65 prefix | 7 | |
| Supply voltage range | VCC | -0.5 | 4 | V | 7 | ||
| Input voltage range (VI range -0.5 to VCC + 0.5) | VI | -0.5 | V | 7 | |||
| Lead temperature 1.6 mm from case for 10 s | 260 | °C | 1.6 mm (1/16 inch) from case for 10 seconds | 7 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 7 | ||
| Power rating | 425 | mW | TA ≤ 25°C, DGK package | 8 | |||
| Power rating | 272 | mW | TA ≤ 70°C, DGK package | 8 | |||
| Power rating | 221 | mW | TA ≤ 85°C, DGK package | 8 | |||
| Supply current, no load | ICC | 4.7 | 8 | mA | VI = 0.8 V or 2 V, No load | 10 | |
| Supply current, RL = 100 Ω | ICC | 9 | 13 | mA | RL = 100 Ω | 10 | |
| Differential output voltage magnitude | VOD | 247 | 340 | 454 | mV | RL = 100 Ω, See Figure 8-2 | 10 |
| Change in differential output voltage magnitude between logic states | ΔVOD | -50 | 50 | mV | RL = 100 Ω, See Figure 8-2 | 10 | |
| Steady-state common-mode output voltage | VOC(SS) | 1.125 | 1.2 | 1.375 | V | See Figure 8-3 | 10 |
| Change in steady-state common-mode output voltage between logic states | ΔVOC(SS) | -50 | 50 | mV | See Figure 8-3 | 10 | |
| Peak-to-peak common-mode output voltage | VOC(PP) | 50 | 150 | mV | See Figure 8-3 | 10 | |
| High-level input current | IIH | 4 | 20 | μA | VIH = 2 | 10 | |
| Low-level input current | IIL | 0.1 | 10 | μA | VIL = 0.8 V | 10 | |
| Short-circuit output current | IOS | -24 | -4 | mA | VO(Y) or VO(Z) = 0 | 10 | |
| Short-circuit output current | IOS | -12 | 12 | mA | VOD = 0 | 10 | |
| High-impedance output current | IOZ | -1 | 1 | μA | VO = 0 or 2.4 V | 10 | |
| Power-off output current | IO(OFF) | -1 | 1 | μA | VCC = 0, VO = 2.4 V | 10 | |
| Input capacitance | Ci | 3 | pF | 10 | |||
| Propagation delay time, low-to-high-level output | tPLH | 0.5 | 1.4 | 2 | ns | RL = 100 Ω, CL = 10 pF, See Figure 8-2 | 11 |
| Propagation delay time, high-to-low-level output | tPHL | 1 | 1.7 | 2.5 | ns | RL = 100 Ω, CL = 10 pF, See Figure 8-2 | 11 |
| Differential output signal rise time (20% to 80%) | tr | 0.4 | 0.5 | 0.6 | ns | RL = 100 Ω, CL = 10 pF, See Figure 8-2 | 11 |
| Differential output signal fall time (80% to 20%) | tf | 0.4 | 0.5 | 0.6 | ns | RL = 100 Ω, CL = 10 pF, See Figure 8-2 | 11 |
| Pulse skew (/tPHL, tPLH/) | tsk(p) | 0.3 | 0.6 | ns | RL = 100 Ω, CL = 10 pF, See Figure 8-2 | 11 | |
| Channel-to-channel output skew | tsk(o) | 0 | 0.3 | ns | RL = 100 Ω, CL = 10 pF, See Figure 8-2 | 11 | |
| Part-to-part skew | tsk(pp) | 800 | ps | 11 | |||
| Propagation delay time, high-impedance-to-high-level output | tPZH | 5.4 | 15 | ns | See Figure 8-4 | 11 | |
| Propagation delay time, high-impedance-to-low-level output | tPZL | 2.5 | 15 | ns | See Figure 8-4 | 11 | |
| Propagation delay time, high-level-to-high-impedance output | tPHZ | 8.1 | 15 | ns | See Figure 8-4 | 11 | |
| Propagation delay time, low-level-to-high-impedance output | tPLZ | 7.3 | 15 | ns | See Figure 8-4 | 11 |
CAD (KiCad official)
- Symbol:
SN65LVDS9638DGK - Footprint:
Package_SO:VSSOP-8_2.3x2mm_P0.5mm - 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)
- 3D model files:
sn65lvds9638dgk-etched.step/sn65lvds9638dgk-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn65lvds9638dgk.step/sn65lvds9638dgk.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (57 pp, sha256
7cfc0e56eb3e8eda, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).