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SN65LVDS34DR
Public Made by Adomby adom
Texas Instruments LVDS ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN65LVDS34DR
Texas Instruments · LVDS ICs · SOIC-8
SN65LVDS34DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Positive supply voltage; recommended operating range 3.0 V to 3.6 V (nom 3.3 V); bypass with 0.1 µF ceramic capacitor as close to pin as possible. |
| 2 | 1Y | output | TTL-compatible output of receiver channel 1; VOH ≥ 2.4 V at IOH = −4 mA, VOL ≤ 0.4 V at IOL = 4 mA; drives to logic-high within 600 ns on failsafe assertion. |
| 3 | 2Y | output | TTL-compatible output of receiver channel 2; VOH ≥ 2.4 V at IOH = −4 mA, VOL ≤ 0.4 V at IOL = 4 mA; drives to logic-high within 600 ns on failsafe assertion. |
| 4 | GND | power_in | Ground reference for all internal circuitry; all voltage values except differential bus voltages are referenced to this terminal. |
| 5 | 2B | input | Inverting (negative) LVDS differential input B of receiver channel 2; VID = V2A − V2B; common-mode range −4 V to 5 V; differential threshold ±50 mV with 50 mV hysteresis; ESD-protected to ±15 kV HBM. |
| 6 | 2A | input | Non-inverting (positive) LVDS differential input A of receiver channel 2; VID = V2A − V2B; common-mode range −4 V to 5 V; differential threshold ±50 mV with 50 mV hysteresis; ESD-protected to ±15 kV HBM. |
| 7 | 1B | input | Inverting (negative) LVDS differential input B of receiver channel 1; VID = V1A − V1B; common-mode range −4 V to 5 V; differential threshold ±50 mV with 50 mV hysteresis; ESD-protected to ±15 kV HBM. |
| 8 | 1A | input | Non-inverting (positive) LVDS differential input A of receiver channel 1; VID = V1A − V1B; common-mode range −4 V to 5 V; differential threshold ±50 mV with 50 mV hysteresis; ESD-protected to ±15 kV HBM. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Interface |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
SN65LVDS34DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
sn65lvds34dr-etched.step/sn65lvds34dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn65lvds34dr.step/sn65lvds34dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
62372f570baf355e, retrieved 2026-09-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-4-6(text+vision), consensusclaude-opus-4-7(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).