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SN65LVDS3486DR

Public Made by Adom

by adom

Texas Instruments LVDS ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232sn65lvds3486drfactory-2.0.0extractor-text

Verified SN65LVDS3486DR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN65LVDS3486DR · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 55-page datasheet
  • ✓distributor: lcsc C2868173, digikey SN65LVDS3486DR-ND, mouser 595-SN65LVDS3486DR
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-zwhnb71n/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn65lvds3486dr.kicad_sym✓ sn65lvds3486dr.kicad_mod✓ sn65lvds3486dr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7h ago
viewers sn65lvds3486dr: viewers · Ray 7h ago
package.json Publish 0.1.0 · Ray 7h ago
page.json Set visibility: public · Ray 7h ago
README.md Publish 0.1.0 · Ray 7h ago
sn65lvds3486dr-etched.glb Publish 0.1.0 · Ray 7h ago
sn65lvds3486dr-etched.step sn65lvds3486dr: factory component page (tier=mfr) · Ray 7h ago
sn65lvds3486dr-hero.glb sn65lvds3486dr: hero GLB from the etched model (keeps the MPN mark) · Ray 7h ago
sn65lvds3486dr-hero.overlay.json Publish 0.1.0 · Ray 7h ago
sn65lvds3486dr.glb Publish 0.1.0 · Ray 7h ago
sn65lvds3486dr.kicad_mod Publish 0.1.0 · Ray 7h ago
sn65lvds3486dr.kicad_sym Publish 0.1.0 · Ray 7h ago
sn65lvds3486dr.lbr Publish 0.1.0 · Ray 7h ago
sn65lvds3486dr.step Publish 0.1.0 · Ray 7h ago
verification.json Verified: Published by the parts factory: tier mfr, 16 pins · Ray 7h ago

SN65LVDS3486DR

Texas Instruments · LVDS ICs · SOIC-16

SN65LVDS3486DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1B input Differential (LVDS) inverting input for channel 1.
2 1A input Differential (LVDS) non-inverting input for channel 1.
3 1Y output LVTTL output signal for channel 1.
4 1,2EN input Enable input for channels 1 and 2; logic high VIH min 2 V, logic low VIL max 0.8 V.
5 2Y output LVTTL output signal for channel 2.
6 2A input Differential (LVDS) non-inverting input for channel 2.
7 2B input Differential (LVDS) inverting input for channel 2.
8 GND power_in Ground.
9 3B input Differential (LVDS) inverting input for channel 3.
10 3A input Differential (LVDS) non-inverting input for channel 3.
11 3Y output LVTTL output signal for channel 3.
12 3,4EN input Enable input for channels 3 and 4; logic high VIH min 2 V, logic low VIL max 0.8 V.
13 4Y output LVTTL output signal for channel 4.
14 4A input Differential (LVDS) non-inverting input for channel 4.
15 4B input Differential (LVDS) inverting input for channel 4.
16 VCC power_in Supply voltage, 3 V to 3.6 V recommended (3.3 V nominal), absolute maximum 4 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Communication Interface Chip/UART/485/232
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 4 V 7
Input voltage range, enables and output VI -0.5 V Enables and output; max VCC + 0.5 V 7
Input voltage range, A or B VI -0.5 4 V A or B 7
Storage temperature Tstg -65 150 °C 7
Electrostatic discharge HBM, bus pins V(ESD) -8000 8000 V HBM per ANSI/ESDA/JEDEC JS-001, bus pins 7
Lead temperature 260 °C 1.6 mm (1/16 inch) from case for 10 seconds 7
Supply voltage VCC 3 3.3 3.6 V 7
High-level input voltage VIH 2 V 1,2EN or 3,4EN 7
Low-level input voltage VIL 0.8 V 1,2EN or 3,4EN 7
Magnitude of differential input voltage /VID/ 0.1 0.6 V 7
Operating free-air temperature TA -40 85 °C SN65 prefix 7
Positive-going differential input voltage threshold VIT+ 100 mV See Figure 7 and Table 1 9
Negative-going differential input voltage threshold VIT- -100 mV See Figure 7 and Table 1 9
High-level output voltage VOH 2.4 V IOH = -8 mA 9
High-level output voltage VOH 2.8 V IOH = -4 mA 9
Low-level output voltage VOL 0.4 V IOL = 8 mA 9
Supply current, enabled ICC 10 18 mA Enabled, No load 9
Supply current, disabled ICC 0.25 0.5 mA Disabled 9
Input current (A or B inputs) II -20 -10 -2 μA VI = 0 9
Input current (A or B inputs) II -3 -1.2 μA VI = 2.4 V 9
Power-off input current (A or B input) II(OFF) 6 20 μA VCC = 0, VI = 3.6 V 9
High-level input current (EN) IIH 10 μA VIH = 2 V 9
Low-level input current (EN) IIL 10 μA VIL = 0.8 V 9
High-impedance output current IOZ -10 10 μA VO = 0 or VCC 9
Propagation delay time, low-to-high-level output tPLH 1.5 2.1 3 ns CL = 10 pF, See Figure 8 10
Propagation delay time, high-to-low-level output tPHL 1.5 2.1 3 ns CL = 10 pF, See Figure 8 10
Pulse skew (/tPHL, tPLH/) tsk(p) 0 0.4 ns CL = 10 pF, See Figure 8 10
Channel-to-channel output skew tsk(o) 0.1 0.3 ns CL = 10 pF, See Figure 8 10
Part-to-part skew tsk(pp) 1 ns CL = 10 pF, See Figure 8 10
Output signal rise time, 20% to 80% tr 0.6 ns CL = 10 pF, See Figure 8 10
Output signal fall time, 80% to 20% tf 0.7 ns CL = 10 pF, See Figure 8 10
Propagation delay time, high-level-to-high-impedance output tPHZ 6.5 12 ns See Figure 9 10
Propagation delay time, low-level-to-high-impedance output tPLZ 5.5 12 ns See Figure 9 10
Propagation delay time, high-impedance-to-high-level output tPZH 8 12 ns See Figure 9 10
Propagation delay time, high-impedance-to-low-level output tPZL 3 12 ns See Figure 9 10

CAD (KiCad official)

  • Symbol: SN65LVDS3486DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn65lvds3486dr-etched.step / sn65lvds3486dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvds3486dr.step / sn65lvds3486dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (55 pp, sha256 890e33b3bb5c4e86, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF