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README

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SN65LVDS3486BDR

Texas Instruments · LVDS ICs · SOIC-16

SN65LVDS3486BDR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1B input Inverting differential receiver input B for channel 1; the bus terminal voltage is recommended to stay between -2 V and 4.4 V, with absolute limits of -4 V to 6 V.
2 1A input Non-inverting differential receiver input A for channel 1; the bus terminal voltage is recommended to stay between -2 V and 4.4 V, and
3 1Y output Channel 1 receiver output, which reaches at least 2.4 V high at -4 mA and at most 0.4 V low at 4 mA, and goes high-impedance when the enable is low.
4 1,2EN input Active-high enable for receivers 1 and 2, with VIH of at least 2 V and VIL of at most 0.8 V; unused enables should be tied to VCC or GND.
5 2Y output Channel 2 receiver output, which reaches at least 2.4 V high at -4 mA and at most 0.4 V low at 4 mA, and goes high-impedance when the enable is low.
6 2A input Non-inverting differential receiver input A for channel 2; the bus terminal voltage is recommended to stay between -2 V and 4.4 V, and
7 2B input Inverting differential receiver input B for channel 2; the bus terminal voltage is recommended to stay between -2 V and 4.4 V, with absolute limits of -4 V to 6 V.
8 GND power_in Network ground terminal to which all voltages except the differential bus voltages are referenced.
9 3B input Inverting differential receiver input B for channel 3; the bus terminal voltage is recommended to stay between -2 V and 4.4 V, with absolute limits of -4 V to 6 V.
10 3A input Non-inverting differential receiver input A for channel 3; the bus terminal voltage is recommended to stay between -2 V and 4.4 V, and
11 3Y output Channel 3 receiver output, which reaches at least 2.4 V high at -4 mA and at most 0.4 V low at 4 mA, and goes high-impedance when the enable is low.
12 3,4EN input Active-high enable for receivers 3 and 4, with VIH of at least 2 V and VIL of at most 0.8 V; unused enables should be tied to VCC or GND.
13 4Y output Channel 4 receiver output, which reaches at least 2.4 V high at -4 mA and at most 0.4 V low at 4 mA, and goes high-impedance when the enable is low.
14 4A input Non-inverting differential receiver input A for channel 4; the bus terminal voltage is recommended to stay between -2 V and 4.4 V, and
15 4B input Inverting differential receiver input B for channel 4; the bus terminal voltage is recommended to stay between -2 V and 4.4 V, with absolute limits of -4 V to 6 V.
16 VCC power_in Supply voltage of 3 V to 3.6 V (3.3 V nominal), with an absolute maximum range of -0.5 V to 4 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Interface
Pins 16

CAD (KiCad official)

  • Symbol: SN65LVDS3486BDR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn65lvds3486bdr-etched.step / sn65lvds3486bdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvds3486bdr.step / sn65lvds3486bdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 a6fe6aaf7a83af37, retrieved 2026-10-11, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF