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SN65LVDS2DBVR

Public Made by Adom

by adom

Texas Instruments LVDS ICs, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs sn65lvds2dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers sn65lvds2dbvr: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md sn65lvds2dbvr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 17d ago
sn65lvds2dbvr-etched.fit.json sn65lvds2dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
sn65lvds2dbvr-etched.glb sn65lvds2dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
sn65lvds2dbvr-etched.step sn65lvds2dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
sn65lvds2dbvr.glb Publish 0.1.0 · Ray 1mo ago
sn65lvds2dbvr.kicad_mod Publish 0.1.0 · Ray 1mo ago
sn65lvds2dbvr.kicad_sym Publish 0.1.0 · Ray 1mo ago
sn65lvds2dbvr.lbr Publish 0.1.0 · Ray 1mo ago
sn65lvds2dbvr.step Publish 0.1.0 · Ray 1mo ago

SN65LVDS2DBVR

Texas Instruments · LVDS ICs · SOT-23-5

SN65LVDS2DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Supply voltage. Recommended operating range 2.4 V to 3.6 V (nominal 3.3 V). Bypass locally with a low-ESR ceramic capacitor.
2 GND power_in Device ground reference. All voltages other than differential bus voltages are referenced to this pin.
3 A input Non-inverting LVDS differential receiver input. Paired with B to form the differential input; differential input threshold is less than 100 mV. Receiver is open-circuit fail-safe.
4 B input Inverting LVDS differential receiver input. Paired with A to form the differential input. On the SN65LVDT2 variant an internal 110 Ω line termination is placed between A and B; SN65LVDS2 has no internal termination.
5 R output LVTTL/LVCMOS single-ended receiver output. Follows the state of the A-B differential input. Output enters high-impedance when VCC is below 1.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Interface
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • SN65LVDS2DBVR
  • SN65LVDS2DBVRDBVT
  • SN65LVDS2DBVRD
  • SN65LVDS2DBVRDR

CAD (KiCad official)

  • Symbol: SN65LVDS2DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: sn65lvds2dbvr-etched.step / sn65lvds2dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvds2dbvr.step / sn65lvds2dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (44 pp, sha256 2830b1f2b732d16f, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF