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Initial commit: component/sn65lvds2d

Ray ·ca27404e2e ·2d ago
2 files changed +244
README.mdadded+45
@@ -0,0 +1,45 @@+# SN65LVDS2D++**Texas Instruments** · LVDS ICs · SOIC-8++SN65LVDS2D from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | B | input | Inverting LVDS receiver input that accepts differential signals with a ±100 mV threshold, up to 600 mV differential, within a common-mode range of 0 V to VCC - 0.8 V. |+| 2 | A | input | Non-inverting LVDS receiver input that accepts differential signals with a ±100 mV threshold, up to 600 mV differential, within a common-mode range of 0 V to VCC - 0.8 V. |+| 3 | NC | unconnected | No internal connection to the lead frame or die; the datasheet recommends grounding NC pins at board level for thermal performance. |+| 4 | NC | unconnected | No internal connection to the lead frame or die; the datasheet recommends grounding NC pins at board level for thermal performance. |+| 5 | GND | power_in | Device ground reference for the supply and all signal voltages. |+| 6 | NC | unconnected | No internal connection to the lead frame or die; the datasheet recommends grounding NC pins at board level for thermal performance. |+| 7 | R | output | LVTTL receiver output; VOH is at least 2.4 V at IOH = -8 mA with VCC = 3 V (1.9 V minimum for 2.6 V to 3.0 V supply), and absolute maximum output current is ±12 mA. |+| 8 | VCC | power_in | Single supply input, recommended 2.4 V to 3.6 V (3.3 V nominal) with absolute maximum rating of 4 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-8 |+| Category | Interface |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `SN65LVDS2D`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)+- 3D model files: `sn65lvds2d-etched.step` / `sn65lvds2d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn65lvds2d.step` / `sn65lvds2d.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn65lvds1) (44 pp, sha256 `f1b54d3df301bfab`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn65lvds2d-datasheet.pdf)
page.jsonadded+199
@@ -0,0 +1,199 @@+{+  "slug": "sn65lvds2d",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments LVDS ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "interface",+    "sn65lvds2d",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "sn65lvds2d.kicad_sym",+    "sn65lvds2d.kicad_mod",+    "sn65lvds2d.glb",+    "sn65lvds2d.step",+    "sn65lvds2d.lbr",+    "docs/hero.png",+    "docs/sn65lvds2d-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "sn65lvds2d-hero.glb",+    "sn65lvds2d-hero.overlay.json"+  ],+  "component": {+    "mpn": "SN65LVDS2D",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-8",+    "pin_count": 8,+    "category": "Interface",+    "subcategory": "LVDS ICs",+    "datasheet": "https://www.ti.com/cn/lit/gpn/sn65lvds1",+    "parts": {+      "symbol": "sn65lvds2d.kicad_sym",+      "footprint": "sn65lvds2d.kicad_mod",+      "model_3d": "sn65lvds2d-hero.glb",+      "model_3d_plain": "sn65lvds2d.glb",+      "model_3d_step": "sn65lvds2d-etched.step",+      "model_3d_step_plain": "sn65lvds2d.step",+      "lbr": "sn65lvds2d.lbr"+    },+    "distributor_links": {+      "lcsc": "C2872842",+      "digikey": "296-12139-5-ND",+      "mouser": "595-SN65LVDS2D"+    },+    "distributor_check": {+      "checked_at": "2026-10-08T00:23:33Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-12139-5-ND",+        "status": "found"+      },+      "mouser": {+        "pn": "595-SN65LVDS2D",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "B",+        "type": "input",+        "description": "Inverting LVDS receiver input that accepts differential signals with a ±100 mV threshold, up to 600 mV differential, within a common-mode range of 0 V to VCC - 0.8 V."+      },+      {+        "number": "2",+        "name": "A",+        "type": "input",+        "description": "Non-inverting LVDS receiver input that accepts differential signals with a ±100 mV threshold, up to 600 mV differential, within a common-mode range of 0 V to VCC - 0.8 V."+      },+      {+        "number": "3",+        "name": "NC",+        "type": "unconnected",+        "description": "No internal connection to the lead frame or die; the datasheet recommends grounding NC pins at board level for thermal performance."+      },+      {+        "number": "4",+        "name": "NC",+        "type": "unconnected",+        "description": "No internal connection to the lead frame or die; the datasheet recommends grounding NC pins at board level for thermal performance."+      },+      {+        "number": "5",+        "name": "GND",+        "type": "power_in",+        "description": "Device ground reference for the supply and all signal voltages."+      },+      {+        "number": "6",+        "name": "NC",+        "type": "unconnected",+        "description": "No internal connection to the lead frame or die; the datasheet recommends grounding NC pins at board level for thermal performance."+      },+      {+        "number": "7",+        "name": "R",+        "type": "output",+        "description": "LVTTL receiver output; VOH is at least 2.4 V at IOH = -8 mA with VCC = 3 V (1.9 V minimum for 2.6 V to 3.0 V supply), and absolute maximum output current is ±12 mA."+      },+      {+        "number": "8",+        "name": "VCC",+        "type": "power_in",+        "description": "Single supply input, recommended 2.4 V to 3.6 V (3.3 V nominal) with absolute maximum rating of 4 V."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: Table 5-2 lists A and B with I/O type 'I' but the description column in the Chinese text calls them ; The pinout comes from Table 5-2 (D column) on page 4 and the D package top view on page 3, and match; The datasheet's integrated 110-ohm termination applies only to SN65LVDT2. The SN65LVDS2D (no termina"+        ],+        "pages_sent": 23,+        "cost_usd": 0.1333,+        "at": "2026-10-08T00:23:17"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/sn65lvds1",+        "pages": 44,+        "sha256": "f1b54d3df301bfab",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "sn65lvds2d.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6,+          4.9,+          1.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "sn65lvds2d-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6,+          4.9,+          1.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "6fc3a23980769e09c0aba4b1ad7621e39fa493e56de78be1bf234e349909fb43",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file