# SN65LVDS1DR

**Texas Instruments** · Pre-ordered Chips · SOIC-8

SN65LVDS1DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supply voltage, recommended 2.4 V to 3.6 V (3.3 V nominal). |
| 2 | D | input | LVTTL driver input signal, 5 V tolerant, with VIH of 2 V to 5 V and VIL of 0 V to 0.8 V. |
| 3 | NC | unconnected | No connect. |
| 4 | GND | power_in | Ground. |
| 5 | NC | unconnected | No connect. |
| 6 | NC | unconnected | No connect. |
| 7 | Y | output | Differential (LVDS) non-inverting output, with a typical differential output voltage of 350 mV into a 100 Ω load. |
| 8 | Z | output | Differential (LVDS) inverting output, with a typical differential output voltage of 350 mV into a 100 Ω load. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 |  | 4 | V | over operating free-air temperature range | 4 |
| Input voltage range (D) | VI | -0.5 |  |  | V | (D); printed max is VCC + 2 | 4 |
| Output voltage (Y or Z) | VO | -0.5 |  | 4 | V | Y or Z | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| HBM ESD, all pins | V(ESD) | -4000 |  | 4000 | V | Human-body model, all pins | 4 |
| HBM ESD, bus pins | V(ESD) | -9000 |  | 9000 | V | Human-body model, bus pins (A, B, Y, Z) | 4 |
| Machine-model ESD | V(ESD) | -400 |  | 400 | V | MM | 4 |
| FCDM ESD | V(ESD) | -1500 |  | 1500 | V | Field-induced-charge device model | 4 |
| Supply voltage | VCC | 2.4 | 3.3 | 3.6 | V |  | 4 |
| High-level input voltage | VIH | 2 |  | 5 | V |  | 4 |
| Low-level input voltage | VIL | 0 |  | 0.8 | V |  | 4 |
| Operating free-air temperature | TA | -40 |  | 85 | °C |  | 4 |
| Differential output voltage magnitude (2.4 ≤ VCC < 3 V) | /VOD/ | 200 | 350 | 454 | mV | RL = 100 Ω, 2.4 ≤ VCC < 3 V | 5 |
| Differential output voltage magnitude (3 ≤ VCC < 3.6 V) | /VOD/ | 247 | 350 | 454 | mV | RL = 100 Ω, 3 ≤ VCC < 3.6 V | 5 |
| Change in differential output voltage magnitude between logic states | Δ/VOD/ | -50 |  | 50 | mV | See Figure 7-2 | 5 |
| Steady-state common-mode output voltage | VOC(SS) | 1.125 |  | 1.375 | V | See Figure 7-2 | 5 |
| Change in steady-state common-mode output voltage between logic states | ΔVOC(SS) | -50 |  | 50 | mV | See Figure 7-2 | 5 |
| Peak-to-peak common-mode output voltage | VOC(PP) |  | 25 | 100 | mV | See Figure 7-2 | 5 |
| Supply current, no load | ICC |  | 2 | 4 | mA | VI = 0 V or VCC, No load | 5 |
| Supply current, RL = 100 Ω | ICC |  | 5.5 | 8 | mA | VI = 0 V or VCC, RL = 100 Ω | 5 |
| High-level input current | IIH |  | 2 | 20 | μA | VIH = 5 V | 5 |
| Low-level input current | IIL |  | 2 | 10 | μA | VIL = 0.8 V | 5 |
| Short-circuit output current (VOY or VOZ = 0) | IOS |  | 3 | 10 | mA | VOY or VOZ = 0 V | 5 |
| Short-circuit output current (VOD = 0) | IOS |  |  | 10 | mA | VOD = 0 V | 5 |
| Power-off output current | IO(OFF) | -1 |  | 1 | μA | VCC = 1.5 V, VO = 3.6 V | 5 |
| Input capacitance | Ci |  | 3 |  | pF | VI = 0.4sin(4E6πt) + 0.5 V | 5 |
| Propagation delay time, low-to-high-level output | tPLH |  | 1.5 | 3.1 | ns | RL = 100 Ω, CL = 10 pF, See Figure 7-5 | 6 |
| Propagation delay time, high-to-low-level output | tPHL |  | 1.8 | 3.1 | ns | RL = 100 Ω, CL = 10 pF, See Figure 7-5 | 6 |
| Differential output signal rise time | tr |  | 0.6 | 1 | ns | RL = 100 Ω, CL = 10 pF, See Figure 7-5 | 6 |
| Differential output signal fall time | tf |  | 0.7 | 1 | ns | RL = 100 Ω, CL = 10 pF, See Figure 7-5 | 6 |
| Pulse skew (/tPHL, tPLH/) | tsk(p) |  |  | 0.3 | ns | RL = 100 Ω, CL = 10 pF, See Figure 7-5 | 6 |
| Junction-to-ambient thermal resistance, D package (8 pins) | RθJA |  | 172.4 |  | °C/W | D package, 8 pins | 5 |
| Power rating, D package |  |  | 725 |  | mW | TA ≤ 25°C | 5 |
| Power rating, D package |  |  | 402 |  | mW | TA ≤ 85°C | 5 |

## CAD (KiCad official)

- Symbol: `SN65LVDS1DR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `sn65lvds1dr-etched.step` / `sn65lvds1dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn65lvds1dr.step` / `sn65lvds1dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn65lvds1.pdf) (44 pp, sha256 `2830b1f2b732d16f`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn65lvds1dr-datasheet.pdf)