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SN65LVDS1D
Public Made by Adomby adom
Texas Instruments Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN65LVDS1D
Texas Instruments · Pre-ordered Chips · SOIC-8
SN65LVDS1D from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supply voltage, recommended range 2.4 V to 3.6 V. |
| 2 | D | input | LVTTL driver input, 5 V tolerant, with VIH of 2 V to 5 V and VIL of 0 V to 0.8 V. |
| 3 | NC | unconnected | No connect. |
| 4 | GND | power_in | Ground. |
| 5 | NC | unconnected | No connect. |
| 6 | NC | unconnected | No connect. |
| 7 | Y | output | Differential (LVDS) non-inverting output, typically 350 mV into a 100 Ω load. |
| 8 | Z | output | Differential (LVDS) inverting output, typically 350 mV into a 100 Ω load. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | 4 | V | All voltage values with respect to network ground terminal | 4 | |
| Input voltage range (D) | VI | -0.5 | V | (D) input; maximum printed as VCC + 2 V | 4 | ||
| Output voltage (Y or Z) | VO | -0.5 | 4 | V | Y or Z output | 4 | |
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Supply voltage | VCC | 2.4 | 3.3 | 3.6 | V | 4 | |
| High-level input voltage | VIH | 2 | 5 | V | 4 | ||
| Low-level input voltage | VIL | 0 | 0.8 | V | 4 | ||
| Operating free-air temperature | TA | -40 | 85 | °C | 4 | ||
| Magnitude of differential input voltage | /VID/ | 0.1 | 0.6 | V | 4 | ||
| Input voltage (any combination of input or common-mode voltage) | 0 | V | Maximum printed as VCC, 0.8 V | 4 | |||
| Differential output voltage magnitude | /VOD/ | 200 | 350 | 454 | mV | RL = 100 Ω, 2.4 ≤ VCC < 3 V | 5 |
| Differential output voltage magnitude | /VOD/ | 247 | 350 | 454 | mV | RL = 100 Ω, 3 ≤ VCC < 3.6 V | 5 |
| Change in differential output voltage magnitude between logic states | Δ/VOD/ | -50 | 50 | mV | See Figure 7-2 | 5 | |
| Steady-state common-mode output voltage | VOC(SS) | 1.125 | 1.375 | V | See Figure 7-2 | 5 | |
| Change in steady-state common-mode output voltage between logic states | ΔVOC(SS) | -50 | 50 | mV | 5 | ||
| Peak-to-peak common-mode output voltage | VOC(PP) | 25 | 100 | mV | 5 | ||
| Short-circuit output current | IOS | 3 | 10 | mA | VOY or VOZ = 0 V | 5 | |
| Short-circuit output current | IOS | 10 | mA | VOD = 0 V | 5 | ||
| Supply current | ICC | 2 | 4 | mA | VI = 0 V or VCC, No load | 5 | |
| Supply current | ICC | 5.5 | 8 | mA | VI = 0 V or VCC, RL = 100 Ω | 5 | |
| High-level input current | IIH | 2 | 20 | μA | VIH = 5 V | 5 | |
| Low-level input current | IIL | 2 | 10 | μA | VIL = 0.8 V | 5 | |
| Power-off output current | IO(OFF) | -1 | 1 | μA | VCC = 1.5 V, VO = 3.6 V | 5 | |
| Propagation delay time, low-to-high-level output | tPLH | 1.5 | 3.1 | ns | RL = 100 Ω, CL = 10 pF, See Figure 7-5 | 6 | |
| Propagation delay time, high-to-low-level output | tPHL | 1.8 | 3.1 | ns | RL = 100 Ω, CL = 10 pF, See Figure 7-5 | 6 | |
| Differential output signal rise time | tr | 0.6 | 1 | ns | 6 | ||
| Differential output signal fall time | tf | 0.7 | 1 | ns | 6 | ||
| Input capacitance | Ci | 3 | pF | VI = 0.4sin(4E6πt) + 0.5 V | 5 | ||
| Pulse skew (/tPHL, tPLH/) | tsk(p) | 0.3 | ns | 6 | |||
| Junction-to-ambient thermal resistance (D, 8 pins) | RθJA | 172.4 | °C/W | D package, 8 pins | 5 | ||
| Power rating (D, 8 pins) | 725 | mW | TA ≤ 25°C | 5 | |||
| Power rating (D, 8 pins) | 402 | mW | TA ≤ 85°C | 5 |
CAD (KiCad official)
- Symbol:
SN65LVDS1D - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
sn65lvds1d-etched.step/sn65lvds1d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn65lvds1d.step/sn65lvds1d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (44 pp, sha256
2830b1f2b732d16f, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).