SN65LVDS104PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	EN1	input	Enable input for channel 1.
2	EN2	input	Enable input for channel 2.
3	EN3	input	Enable input for channel 3.
4	VCC	power_in	Supply voltage, 3 V minimum, 3.3 V nominal and 3.6 V maximum per the recommended operating conditions.
5	GND	power_in	Ground reference for the device.
6	A	input	LVDS input, positive for the SN65LVDS104, which accepts differential input levels of ±100 mV.
7	B	input	LVDS input, negative for the SN65LVDS104; this pin is NC on the SN65LVDS105.
8	EN4	input	Enable input for channel 4.
9	4Z	output	LVDS output, negative, channel 4, with driver outputs high-impedance when disabled.
10	4Y	output	LVDS output, positive, channel 4, with driver outputs high-impedance when disabled.
11	3Z	output	LVDS output, negative, channel 3, with driver outputs high-impedance when disabled.
12	3Y	output	LVDS output, positive, channel 3, with driver outputs high-impedance when disabled.
13	2Z	output	LVDS output, negative, channel 2, with driver outputs high-impedance when disabled.
14	2Y	output	LVDS output, positive, channel 2, with driver outputs high-impedance when disabled.
15	1Z	output	LVDS output, negative, channel 1, with driver outputs high-impedance when disabled.
16	1Y	output	LVDS output, positive, channel 1, with driver outputs high-impedance when disabled.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	Interface
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	-0.5		4	V		4
Voltage A, B, Y or Z		-0.5		4	V		4
Lead temperature				260	°C	1.6 mm (1/16 inch) from case for 10 seconds	4
Storage temperature	Tstg	-65		150	°C		4
Supply voltage	VCC	3	3.3	3.6	V		4
High-level input voltage	VIH	2			V		4
Low-level input voltage	VIL			0.8	V		4
Voltage at any bus terminal (separately or common-mode)	VI or VIC	0			V	maximum printed as VCC-0.8	4
Operating free-air temperature	TA	-40		85	°C		4
Junction-to-ambient thermal resistance	RθJA		101.6		°C/W	PW (TSSOP) 16 pins	4
Junction-to-case (top) thermal resistance	RθJC(top)		29.2		°C/W	PW (TSSOP) 16 pins	4
Junction-to-board thermal resistance	RθJB		47.3		°C/W	PW (TSSOP) 16 pins	4
Junction-to-top characterization parameter	ψJT		1.4		°C/W	PW (TSSOP) 16 pins	4
Junction-to-board characterization parameter	ψJB		46.6		°C/W	PW (TSSOP) 16 pins	4
Positive-going differential input voltage threshold	VIT+			100	mV	See Figure 13 and Table 1	5
Negative-going differential input voltage threshold	VIT-			-100	mV	See Figure 13 and Table 1	5
Differential output voltage magnitude	/VOD/	247	340	454	mV	RL = 100 Ω, VID = ± 100 mV	5
Change in differential output voltage magnitude between logic states	Δ/VOD/	-50		50	mV	RL = 100 Ω, VID = ± 100 mV	5
Steady-state common-mode output voltage	VOC(SS)	1.125		1.375	V		5
Change in steady-state common-mode output voltage between logic states	ΔVOC(SS)	-50		50	mV		5
Peak-to-peak common-mode output voltage	VOC(PP)	25		150	mV		5
Supply current, enabled	ICC		23	35	mA	Enabled, RL = 100 Ω	5
Supply current, disabled	ICC		3	8	mA	Disabled	5
Input current (A or B inputs)	II	-2	-11	-20	µA	VI = 0 V	5
Input current (A or B inputs)	II		-1.2	-3	µA	VI = 2.4 V	5
Power-off input current	II(OFF)			20	µA	VCC = 1.5 V, VI = 2.4 V	5
High-level input current (enables)	IIH			20	µA	VIH = 2 V	5
Low-level input current (enables)	IIL			10	µA	VIL = 0.8 V	5
Short-circuit output current	IOS	-10		10	mA	VOY or VOZ = 0 V	5
High-impedance output current	IOZ	-1		1	µA	VO = 0 V or 2.4 V	5
Power-off output current	IO(OFF)	-1		1	µA	VCC = 1.5 V, VO = 2.4 V	5
Input capacitance (A or B inputs)	CIN		3		pF	VI = 0.4 sin (4E6πt) + 0.5 V	5
Output capacitance (Y or Z outputs)	CO		9.4		pF	VI = 0.4 sin (4E6πt) + 0.5 V, Disabled	5
Propagation delay time, low-to-high-level output	tPLH	2.4	3.2	4.2	ns	RL = 100 Ω, CL = 10 pF	6
Propagation delay time, high-to-low-level output	tPHL	2.2	3.1	4.2	ns	RL = 100 Ω, CL = 10 pF	6
Differential output signal rise time	tr	0.3	0.8	1.2	ns	RL = 100 Ω, CL = 10 pF	6
Differential output signal fall time	tf	0.3	0.8	1.2	ns	RL = 100 Ω, CL = 10 pF	6
Pulse skew (/tPHL - tPLH/)	tsk(p)		150	500	ps	RL = 100 Ω, CL = 10 pF	6
Channel-to-channel output skew	tsk(o)		20	100	ps	RL = 100 Ω, CL = 10 pF	6
Part-to-part skew	tsk(pp)			1.5	ns		6
Propagation delay time, high-impedance-to-high-level output	tPZH		7.2	15	ns	See Figure 17	6
Propagation delay time, high-impedance-to-low-level output	tPZL		8.4	15	ns	See Figure 17	6
Propagation delay time, high-level-to-high-impedance output	tPHZ		3.6	15	ns	See Figure 17	6
Propagation delay time, low-level-to-high-impedance output	tPLZ		6	15	ns	See Figure 17	6

CAD (KiCad official)

Symbol: SN65LVDS104PWR
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: sn65lvds104pwr-etched.step / sn65lvds104pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvds104pwr.step / sn65lvds104pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (42 pp, sha256 4f692df78fe69a72, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

SN65LVDS104PWR

Verified SN65LVDS104PWR

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3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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