Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN65LVDS100DGKR

Texas Instruments · Signal Buffers, Repeaters, Splitters · VSSOP-8-0.65mm

SN65LVDS100DGKR from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect. Pin is not internally bonded; leave floating or tie as convenient for layout.
2 A input Differential non-inverting input. Accepts LVDS/LVPECL/CML signals; input voltage range 0 V to 4 V,
3 B input Differential inverting input. Accepts LVDS/LVPECL/CML signals; input voltage range 0 V to 4 V,
4 VBB output Voltage reference output, typically VCC - 1.35 V. Useful for biasing single-ended 3.3-V PECL inputs. Source/sink capability limited to -400 uA / 12 uA; leave open if unused.
5 GND power_in Device ground reference (0 V). Connect to system ground with low-impedance return.
6 Z output Differential inverting LVDS output. Typical
7 Y output Differential non-inverting LVDS output. Typical
8 VCC power_in Supply voltage. 3.0 V to 3.6 V (3.3 V nominal). Typical supply current 25 mA (no-load, no input). Bypass locally to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VSSOP-8-0.65mm
Category Interface
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • SN65LVDS100DGKR
  • SN65LVDS100DGKRD
  • SN65LVDS100DGKRDR

CAD (KiCad official)

  • Symbol: SN65LVDS100DGKR
  • Footprint: Package_SO:VSSOP-8_2.3x2mm_P0.5mm
  • 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)
  • 3D model files: sn65lvds100dgkr-etched.step / sn65lvds100dgkr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvds100dgkr.step / sn65lvds100dgkr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 c18e0bae1214905c, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF