component
SN65LVDS048APW
Public Made by Adomby adom
Texas Instruments LVDS ICs, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# SN65LVDS048APW++**Texas Instruments** · LVDS ICs · TSSOP-16++SN65LVDS048APW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RIN1- | input | Receiver 1 inverting LVDS differential input; valid output for |VID| ≥ 100 mV within common-mode range, input range GND to 3 V. |+| 2 | RIN1+ | input | Receiver 1 non-inverting LVDS differential input; valid output for |VID| ≥ 100 mV within common-mode range, input range GND to 3 V. |+| 3 | RIN2+ | input | Receiver 2 non-inverting LVDS differential input; valid output for |VID| ≥ 100 mV within common-mode range, input range GND to 3 V. |+| 4 | RIN2- | input | Receiver 2 inverting LVDS differential input; valid output for |VID| ≥ 100 mV within common-mode range, input range GND to 3 V. |+| 5 | RIN3- | input | Receiver 3 inverting LVDS differential input; valid output for |VID| ≥ 100 mV within common-mode range, input range GND to 3 V. |+| 6 | RIN3+ | input | Receiver 3 non-inverting LVDS differential input; valid output for |VID| ≥ 100 mV within common-mode range, input range GND to 3 V. |+| 7 | RIN4+ | input | Receiver 4 non-inverting LVDS differential input; valid output for |VID| ≥ 100 mV within common-mode range, input range GND to 3 V. |+| 8 | RIN4- | input | Receiver 4 inverting LVDS differential input; valid output for |VID| ≥ 100 mV within common-mode range, input range GND to 3 V. |+| 9 | EN̅ | input | Active-low receiver enable input; outputs are enabled when EN is high or EN̅ is low, with VIH 2.0 V min and VIL 0.8 V max. |+| 10 | ROUT4 | tri_state | Receiver 4 LVCMOS output, 3-state when disabled; VOH 2.7 V min at IOH = -0.4 mA, VOL 0.25 V max at IOL = 2 mA. |+| 11 | ROUT3 | tri_state | Receiver 3 LVCMOS output, 3-state when disabled; VOH 2.7 V min at IOH = -0.4 mA, VOL 0.25 V max at IOL = 2 mA. |+| 12 | GND | power_in | Ground reference for the device. |+| 13 | VCC | power_in | Supply voltage pin, 3 V to 3.6 V recommended (3.3 V nominal), absolute maximum 4 V. |+| 14 | ROUT2 | tri_state | Receiver 2 LVCMOS output, 3-state when disabled; VOH 2.7 V min at IOH = -0.4 mA, VOL 0.25 V max at IOL = 2 mA. |+| 15 | ROUT1 | tri_state | Receiver 1 LVCMOS output, 3-state when disabled; VOH 2.7 V min at IOH = -0.4 mA, VOL 0.25 V max at IOL = 2 mA. |+| 16 | EN | input | Active-high receiver enable input; outputs are enabled when EN is high, with VIH 2.0 V min and VIL 0.8 V max. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Interface |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `SN65LVDS048APW`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `sn65lvds048apw-etched.step` / `sn65lvds048apw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn65lvds048apw.step` / `sn65lvds048apw.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn65lvds048a.pdf) (15 pp, sha256 `7708d93a62e38923`, retrieved 2026-10-07, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn65lvds048apw-datasheet.pdf)
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valid output for |VID| ≥ 100 mV within common-mode range, input range GND to 3 V."+ },+ {+ "number": "2",+ "name": "RIN1+",+ "type": "input",+ "description": "Receiver 1 non-inverting LVDS differential input; valid output for |VID| ≥ 100 mV within common-mode range, input range GND to 3 V."+ },+ {+ "number": "3",+ "name": "RIN2+",+ "type": "input",+ "description": "Receiver 2 non-inverting LVDS differential input; valid output for |VID| ≥ 100 mV within common-mode range, input range GND to 3 V."+ },+ {+ "number": "4",+ "name": "RIN2–",+ "type": "input",+ "description": "Receiver 2 inverting LVDS differential input; valid output for |VID| ≥ 100 mV within common-mode range, input range GND to 3 V."+ },+ {+ "number": "5",+ "name": "RIN3–",+ "type": "input",+ "description": "Receiver 3 inverting LVDS differential input; valid output for |VID| ≥ 100 mV within common-mode range, input range GND to 3 V."+ },+ {+ "number": "6",+ "name": "RIN3+",+ "type": "input",+ "description": "Receiver 3 non-inverting LVDS differential input; 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VOH 2.7 V min at IOH = -0.4 mA, VOL 0.25 V max at IOL = 2 mA."+ },+ {+ "number": "12",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "13",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage pin, 3 V to 3.6 V recommended (3.3 V nominal), absolute maximum 4 V."+ },+ {+ "number": "14",+ "name": "ROUT2",+ "type": "tri_state",+ "description": "Receiver 2 LVCMOS output, 3-state when disabled; VOH 2.7 V min at IOH = -0.4 mA, VOL 0.25 V max at IOL = 2 mA."+ },+ {+ "number": "15",+ "name": "ROUT1",+ "type": "tri_state",+ "description": "Receiver 1 LVCMOS output, 3-state when disabled; VOH 2.7 V min at IOH = -0.4 mA, VOL 0.25 V max at IOL = 2 mA."+ },+ {+ "number": "16",+ "name": "EN",+ "type": "input",+ "description": "Active-high receiver enable input; outputs are enabled when EN is high, with VIH 2.0 V min and VIL 0.8 V max."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pinout diagram on page 1 shows only partial labels for the right-side pins (16-9). The differential "+ ],+ "pages_sent": 15,+ "cost_usd": 0.2186,+ "at": "2026-10-07T08:24:32"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn65lvds048a.pdf",+ "pages": 15,+ "sha256": "7708d93a62e38923",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn65lvds048apw.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn65lvds048apw-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "c0a017a869bae6bf31827c04cf2d18fd6a009ab192765ea70102c5ac2082e4c0",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}