SN65LVDM180PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	Not internally connected, as marked NC on the SN65LVDM180 TSSOP (PW) top-view pin diagram.
2	R	output	Receiver output that reflects the differential input A-B; the receiver detects a 50 mV differential input with up to 1 V of ground potential difference between transmitter and receiver.
3	RE	input	Receiver enable input with LVTTL levels that are 5-V tolerant; active polarity is not stated in the provided pages.
4	DE	input	Driver enable input with LVTTL levels that are 5-V tolerant; the driver is high impedance when disabled.
5	D	input	Driver data input with LVTTL levels that are 5-V tolerant, used to set the state of the differential driver outputs Y and Z.
6	GND	power_in	Ground reference pin; the device tolerates up to 1 V of ground potential difference between transmitter and receiver.
7	GND	power_in	Ground reference pin; the device tolerates up to 1 V of ground potential difference between transmitter and receiver.
8	NC	unconnected	Not internally connected, as marked NC on the SN65LVDM180 TSSOP (PW) top-view pin diagram.
9	Y	output	Non-inverting LVDS driver output; the driver supplies a minimum differential output magnitude of 247 mV across a 50-Ω load.
10	Z	output	Inverting LVDS driver output; the driver supplies a minimum differential output magnitude of 247 mV across a 50-Ω load.
11	B	input	Receiver input, complementary to A; a differential input of 50 mV is detected with up to 1 V ground difference.
12	A	input	Receiver input, non-inverting side of the differential receiver pair with B; a differential input of 50 mV is detected.
13	VCC	power_in	Positive supply pin; the device operates from a single 3.3-V supply.
14	VCC	power_in	Positive supply pin; the device operates from a single 3.3-V supply.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-14
Category	Interface ICs
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	3	3.3	3.6	V		4
Driver output voltage	VO	0		2.4	V		4
High-level input voltage	VIH	2			V		4
Low-level input voltage	VIL			0.8	V		4
Magnitude of differential input voltage	/VID/	0.1		0.6	V		4
Operating free-air temperature	TA	-40		85	°C		4
Supply voltage range	VCC	-0.5		4	V		4
Voltage range, D, R, DE, RE		-0.5		6	V		4
Voltage range, Y, Z, A, B		-0.5		4	V		4
Electrostatic discharge, Y, Z, A, B and GND				12	kV	Class 3, A	4
Electrostatic discharge, Y, Z, A, B and GND				600	V	Class 3, B	4
Storage temperature range		-65		150	°C		4
Power rating, PW (14) package				736	mW	TA ≤ 25°C	4
Power rating, PW (14) package				383	mW	TA = 85°C	4
Supply current, driver enabled, receiver disabled	ICC		9	13	mA	Driver enabled, receiver disabled, RL = 50 Ω	5
Supply current, driver disabled, receiver enabled	ICC		1.7	5	mA	Driver disabled, receiver enabled, no load	5
Supply current, disabled	ICC		0.5	2	mA	Disabled	5
Supply current, drivers and receivers enabled	ICC		19	27	mA	Drivers and receivers enabled, no receiver loads, driver RL = 50 Ω	5
Differential output voltage magnitude	/VOD/	247	340	454	mV	RL = 50 Ω, See Figure 1 and Figure 2	5
Change in differential output voltage magnitude between logic states	Δ/VOD/	-50		50	mV	RL = 50 Ω, See Figure 1 and Figure 2	5
Steady-state common-mode output voltage	VOC(SS)	1.125	1.2	1.375	V		5
Change in steady-state common-mode output voltage between logic states	ΔVOC(SS)	-50		50	mV	See Figure 3	5
Peak-to-peak common-mode output voltage	VOC(PP)		50	150	mV		5
High-level input current, DE	IIH	-20		-0.5	µA	VIH = 5 V	5
High-level input current, D	IIH	2		20	µA	VIH = 5 V	5
Low-level input current, DE	IIL	-10		-0.5	µA	VIL = 0.8 V	5
Low-level input current, D	IIL	2		10	µA	VIL = 0.8 V	5
Short-circuit output current	IOS	7		10	mA	VOY or VOZ = 0 V	5
High-impedance output current	IOZ	-47		47	µA	VO = 0 V or 2.4 V, other output at 1.2 V, DE at 0.8 V	5
Power-off output current	IO(OFF)	-47		47	µA	VCC = 0 V, VO = 0 V or 2.4 V, other output at 1.2 V, DE at 0.8 V	5
Positive-going differential input voltage threshold	VIT+			50	mV	See Figure 5 and Table 2	6
Negative-going differential input voltage threshold	VIT-	-50			mV	See Figure 5 and Table 2	6
High-level output voltage	VOH	2.4			V	IOH = -8 mA	6
Low-level output voltage	VOL			0.4	V	IOL = 8 mA	6
Input current (A or B inputs)	II	-20		-11	µA	VI = 0	6
Input current (A or B inputs)	II	-3		-1.2	µA	VI = 2.4 V	6
Power-off input current (A or B inputs)	II(OFF)	-20		20	µA	VCC = 0	6
High-level input current (enables)	IIH			10	µA	VIH = 5 V	6
Low-level input current (enables)	IIL			10	µA	VIL = 0.8 V	6
High-impedance output current	IOZ	-10		10	µA	VO = 0 or 5 V	6
Propagation delay time, low-to-high-level output (receiver)	tPLH		3.7	4.5	ns	CL = 10 pF, See Figure 6	7
Propagation delay time, high-to-low-level output (receiver)	tPHL		3.7	4.5	ns	CL = 10 pF, See Figure 6	7
Part-to-part skew	tsk(pp)			1	ns		7
Output signal rise time (receiver)	tr		0.7	1.5	ns	CL = 10 pF, See Figure 6	7
Output signal fall time (receiver)	tf		0.9	1.5	ns	CL = 10 pF, See Figure 6	7
Propagation delay time, high-level-to-high-impedance output (receiver)	tPZH			2.5	ns	See Figure 7	7
Propagation delay time, low-level-to-low-impedance output (receiver)	tPZL			2.5	ns	See Figure 7	7
Propagation delay time, high-impedance-to-high-level output (receiver)	tPHZ			7	ns	See Figure 7	7
Propagation delay time, low-impedance-to-high-level output (receiver)	tPLZ			4	ns	See Figure 7	7
Propagation delay time, low-to-high-level output (driver)	tPLH		1.7	2.7	ns	RL = 50Ω, CL = 10 pF, See Figure 6	6
Propagation delay time, high-to-low-level output (driver)	tPHL		1.7	2.7	ns	RL = 50Ω, CL = 10 pF, See Figure 6	6
Differential output signal rise time (driver)	tr		0.6	1	ns	RL = 50Ω, CL = 10 pF, See Figure 6	6
Differential output signal fall time (driver)	tf		0.6	1	ns	RL = 50Ω, CL = 10 pF, See Figure 6	6
Pulse skew (/tPHL - tPLH/) (driver)	tsk(p)			250	ps		6
Channel-to-channel output skew (driver)	tsk(o)			100	ps		6
Propagation delay time, high-impedance-to-high-level output (driver)	tPZH		6	10	ns	See Figure 7	6
Propagation delay time, high-impedance-to-low-level output (driver)	tPZL		6	10	ns	See Figure 7	6
Propagation delay time, high-level-to-high-impedance output (driver)	tPHZ		4	10	ns	See Figure 7	6
Propagation delay time, low-level-to-high-impedance output (driver)	tPLZ		5	10	ns	See Figure 7	6

CAD (KiCad official)

Symbol: SN65LVDM180PWR
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: sn65lvdm180pwr-etched.step / sn65lvdm180pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvdm180pwr.step / sn65lvdm180pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (41 pp, sha256 37c047cec245475d, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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SN65LVDM180PWR

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