component
SN65LVDM051PWR
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Texas Instruments LVDS ICs, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# SN65LVDM051PWR++**Texas Instruments** · LVDS ICs · TSSOP-16++SN65LVDM051PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1B | input | Receiver 1 inverting differential line input (B) with 50-mV input threshold (VID) and open-circuit failsafe. |+| 2 | 1A | input | Receiver 1 non-inverting differential line input (A); output R is high for VID = VA - VB ≥ 50 mV. |+| 3 | 1R | output | Receiver 1 logic output, high for VID ≥ 50 mV, low for VID ≤ -50 mV, and high when inputs are open. |+| 4 | 1DE | input | Driver 1 enable input (LVTTL, 5-V tolerant); driver output is high impedance when disabled. |+| 5 | 2R | output | Receiver 2 logic output, high for VID ≥ 50 mV, low for VID ≤ -50 mV, and high when inputs are open. |+| 6 | 2A | input | Receiver 2 non-inverting differential line input (A) with 50-mV input threshold. |+| 7 | 2B | input | Receiver 2 inverting differential line input (B) with 50-mV input threshold. |+| 8 | GND | power_in | Ground; receivers tolerate up to 1 V of ground potential difference between transmitter and receiver. |+| 9 | 2D | input | Driver 2 logic input (LVTTL, 5-V tolerant); open input drives Y low and Z high. |+| 10 | 2Y | output | Driver 2 non-inverting differential line output, typically 340 mV into a 50-Ω load. |+| 11 | 2Z | output | Driver 2 inverting differential line output, typically 340 mV into a 50-Ω load. |+| 12 | 2DE | input | Driver 2 enable input (LVTTL, 5-V tolerant); driver output is high impedance when disabled. |+| 13 | 1Z | output | Driver 1 inverting differential line output, typically 340 mV into a 50-Ω load. |+| 14 | 1Y | output | Driver 1 non-inverting differential line output, typically 340 mV into a 50-Ω load. |+| 15 | 1D | input | Driver 1 logic input (LVTTL, 5-V tolerant); open input drives Y low and Z high. |+| 16 | VCC | power_in | Single 3.3-V supply; drivers are high impedance when VCC < 1.5 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Interface |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `SN65LVDM051PWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `sn65lvdm051pwr-etched.step` / `sn65lvdm051pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn65lvdm051pwr.step` / `sn65lvdm051pwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn65lvdm051.pdf) (41 pp, sha256 `da1071ed34b491ab`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn65lvdm051pwr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "sn65lvdm051pwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn65lvdm051pwr.kicad_sym",+ "sn65lvdm051pwr.kicad_mod",+ "sn65lvdm051pwr.glb",+ "sn65lvdm051pwr.step",+ "sn65lvdm051pwr.lbr",+ "docs/hero.png",+ "docs/sn65lvdm051pwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn65lvdm051pwr-hero.glb",+ "sn65lvdm051pwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN65LVDM051PWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Interface",+ "subcategory": "LVDS ICs",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn65lvdm051.pdf",+ "parts": {+ "symbol": "sn65lvdm051pwr.kicad_sym",+ "footprint": "sn65lvdm051pwr.kicad_mod",+ "model_3d": "sn65lvdm051pwr-hero.glb",+ "model_3d_plain": "sn65lvdm051pwr.glb",+ "model_3d_step": "sn65lvdm051pwr-etched.step",+ "model_3d_step_plain": "sn65lvdm051pwr.step",+ "lbr": "sn65lvdm051pwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2877021",+ "digikey": "296-52704-2-ND",+ "mouser": "595-SN65LVDM051PWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T17:09:37Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-52704-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-SN65LVDM051PWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "1B",+ "type": "input",+ "description": "Receiver 1 inverting differential line input (B) with 50-mV input threshold (VID) and open-circuit failsafe."+ },+ {+ "number": "2",+ "name": "1A",+ "type": "input",+ "description": "Receiver 1 non-inverting differential line input (A); output R is high for VID = VA - VB ≥ 50 mV."+ },+ {+ "number": "3",+ "name": "1R",+ "type": "output",+ "description": "Receiver 1 logic output, high for VID ≥ 50 mV, low for VID ≤ -50 mV, and high when inputs are open."+ },+ {+ "number": "4",+ "name": "1DE",+ "type": "input",+ "description": "Driver 1 enable input (LVTTL, 5-V tolerant); driver output is high impedance when disabled."+ },+ {+ "number": "5",+ "name": "2R",+ "type": "output",+ "description": "Receiver 2 logic output, high for VID ≥ 50 mV, low for VID ≤ -50 mV, and high when inputs are open."+ },+ {+ "number": "6",+ "name": "2A",+ "type": "input",+ "description": "Receiver 2 non-inverting differential line input (A) with 50-mV input threshold."+ },+ {+ "number": "7",+ "name": "2B",+ "type": "input",+ "description": "Receiver 2 inverting differential line input (B) with 50-mV input threshold."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; receivers tolerate up to 1 V of ground potential difference between transmitter and receiver."+ },+ {+ "number": "9",+ "name": "2D",+ "type": "input",+ "description": "Driver 2 logic input (LVTTL, 5-V tolerant); open input drives Y low and Z high."+ },+ {+ "number": "10",+ "name": "2Y",+ "type": "output",+ "description": "Driver 2 non-inverting differential line output, typically 340 mV into a 50-Ω load."+ },+ {+ "number": "11",+ "name": "2Z",+ "type": "output",+ "description": "Driver 2 inverting differential line output, typically 340 mV into a 50-Ω load."+ },+ {+ "number": "12",+ "name": "2DE",+ "type": "input",+ "description": "Driver 2 enable input (LVTTL, 5-V tolerant); driver output is high impedance when disabled."+ },+ {+ "number": "13",+ "name": "1Z",+ "type": "output",+ "description": "Driver 1 inverting differential line output, typically 340 mV into a 50-Ω load."+ },+ {+ "number": "14",+ "name": "1Y",+ "type": "output",+ "description": "Driver 1 non-inverting differential line output, typically 340 mV into a 50-Ω load."+ },+ {+ "number": "15",+ "name": "1D",+ "type": "input",+ "description": "Driver 1 logic input (LVTTL, 5-V tolerant); open input drives Y low and Z high."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Single 3.3-V supply; drivers are high impedance when VCC < 1.5 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pinout was reconstructed from garbled text extraction of the SN65LVDM051D/PW top-view drawing (p; The datasheet covers SN65LVDM051PW (TSSOP PW 16) but page 1 does not show a standalone PW16 top-view; Pin descriptions were written from the function tables and electrical characteristics for the SN65LV",+ "4/16 pins cited to the wrong page (name found elsewhere): ['4:1Y@p5', '10:2Z@p5', '12:2Y@p5', '14:1Z@p5']"+ ],+ "pages_sent": 41,+ "cost_usd": 0.0872,+ "at": "2026-10-08T17:09:22"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn65lvdm051.pdf",+ "pages": 41,+ "sha256": "da1071ed34b491ab",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn65lvdm051pwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn65lvdm051pwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e927ace8a5a2a7a7cf86ac8db1a2affdcaa33ea095a322a86719d011def07c9d",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}