Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN65LVDM051PWR

Texas Instruments · LVDS ICs · TSSOP-16

SN65LVDM051PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1B input Receiver 1 inverting differential line input (B) with 50-mV input threshold (VID) and open-circuit failsafe.
2 1A input Receiver 1 non-inverting differential line input (A); output R is high for VID = VA - VB ≥ 50 mV.
3 1R output Receiver 1 logic output, high for VID ≥ 50 mV, low for VID ≤ -50 mV, and high when inputs are open.
4 1DE input Driver 1 enable input (LVTTL, 5-V tolerant); driver output is high impedance when disabled.
5 2R output Receiver 2 logic output, high for VID ≥ 50 mV, low for VID ≤ -50 mV, and high when inputs are open.
6 2A input Receiver 2 non-inverting differential line input (A) with 50-mV input threshold.
7 2B input Receiver 2 inverting differential line input (B) with 50-mV input threshold.
8 GND power_in Ground; receivers tolerate up to 1 V of ground potential difference between transmitter and receiver.
9 2D input Driver 2 logic input (LVTTL, 5-V tolerant); open input drives Y low and Z high.
10 2Y output Driver 2 non-inverting differential line output, typically 340 mV into a 50-Ω load.
11 2Z output Driver 2 inverting differential line output, typically 340 mV into a 50-Ω load.
12 2DE input Driver 2 enable input (LVTTL, 5-V tolerant); driver output is high impedance when disabled.
13 1Z output Driver 1 inverting differential line output, typically 340 mV into a 50-Ω load.
14 1Y output Driver 1 non-inverting differential line output, typically 340 mV into a 50-Ω load.
15 1D input Driver 1 logic input (LVTTL, 5-V tolerant); open input drives Y low and Z high.
16 VCC power_in Single 3.3-V supply; drivers are high impedance when VCC < 1.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Interface
Pins 16

CAD (KiCad official)

  • Symbol: SN65LVDM051PWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn65lvdm051pwr-etched.step / sn65lvdm051pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvdm051pwr.step / sn65lvdm051pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 da1071ed34b491ab, retrieved 2026-10-08, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF