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SN65LVDM050QDG4Q1
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Texas Instruments LVDS ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# SN65LVDM050QDG4Q1++**Texas Instruments** · LVDS ICs · SOIC-16++SN65LVDM050QDG4Q1 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1B | input | Inverting (B) differential input of receiver 1, which resolves a differential input of ±50 mV (VIT+ = 50 mV, VIT− = −50 mV) with open-circuit fail-safe. |+| 2 | 1A | input | Non-inverting (A) differential input of receiver 1, which detects a 50 mV differential input with up to 1 V ground potential difference between transmitter and receiver. |+| 3 | 1R | output | LVTTL output of receiver 1 that is high impedance when RE is high, with VOH of at least 2.4 V at −8 mA and VOL of at most 0.4 V at 8 mA. |+| 4 | RE | input | Active-low receiver enable shared by both receivers; a high level places the R outputs in high impedance, with VIH of at least 2 V and VIL of at most 0.8 V. |+| 5 | 2R | output | LVTTL output of receiver 2 that is high impedance when RE is high, with VOH of at least 2.4 V at −8 mA and VOL of at most 0.4 V at 8 mA. |+| 6 | 2A | input | Non-inverting (A) differential input of receiver 2, which detects a 50 mV differential input with up to 1 V ground potential difference between transmitter and receiver. |+| 7 | 2B | input | Inverting (B) differential input of receiver 2, which resolves a differential input of ±50 mV (VIT+ = 50 mV, VIT− = −50 mV) with open-circuit fail-safe. |+| 8 | GND | power_in | Device ground; all voltages except differential I/O bus voltages are referenced to this network ground terminal. |+| 9 | 2D | input | Driver 2 LVTTL data input, 5 V tolerant, with VIH of at least 2 V and VIL of at most 0.8 V. |+| 10 | 2Y | output | Non-inverting LVDS output of driver 2, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V. |+| 11 | 2Z | output | Inverting LVDS output of driver 2, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V. |+| 12 | DE | input | Active-high driver enable shared by both drivers; a low level forces Y and Z of both drivers to high impedance, with VIH of at least 2 V and VIL of at most 0.8 V. |+| 13 | 1Z | output | Inverting LVDS output of driver 1, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V. |+| 14 | 1Y | output | Non-inverting LVDS output of driver 1, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V. |+| 15 | 1D | input | Driver 1 LVTTL data input, 5 V tolerant, with VIH of at least 2 V and VIL of at most 0.8 V. |+| 16 | VCC | power_in | Single supply pin, specified from 3 V to 3.6 V with 3.3 V nominal. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Interface |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `SN65LVDM050QDG4Q1`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `sn65lvdm050qdg4q1-etched.step` / `sn65lvdm050qdg4q1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn65lvdm050qdg4q1.step` / `sn65lvdm050qdg4q1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn65lvdm051-q1) (24 pp, sha256 `bbb259bd55ba22b0`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn65lvdm050qdg4q1-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "sn65lvdm050qdg4q1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn65lvdm050qdg4q1.kicad_sym",+ "sn65lvdm050qdg4q1.kicad_mod",+ "sn65lvdm050qdg4q1.glb",+ "sn65lvdm050qdg4q1.step",+ "sn65lvdm050qdg4q1.lbr",+ "docs/hero.png",+ "docs/sn65lvdm050qdg4q1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn65lvdm050qdg4q1-hero.glb",+ "sn65lvdm050qdg4q1-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN65LVDM050QDG4Q1",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Interface",+ "subcategory": "LVDS ICs",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn65lvdm051-q1",+ "parts": {+ "symbol": "sn65lvdm050qdg4q1.kicad_sym",+ "footprint": "sn65lvdm050qdg4q1.kicad_mod",+ "model_3d": "sn65lvdm050qdg4q1-hero.glb",+ "model_3d_plain": "sn65lvdm050qdg4q1.glb",+ "model_3d_step": "sn65lvdm050qdg4q1-etched.step",+ "model_3d_step_plain": "sn65lvdm050qdg4q1.step",+ "lbr": "sn65lvdm050qdg4q1.lbr"+ },+ "distributor_links": {+ "lcsc": "C1545317",+ "digikey": "2156-SN65LVDM050QDG4Q1-ND",+ "mouser": "595-N65LVDM050QDG4Q1"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T14:39:43Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "2156-SN65LVDM050QDG4Q1-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-N65LVDM050QDG4Q1",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "1B",+ "type": "input",+ "description": "Inverting (B) differential input of receiver 1, which resolves a differential input of ±50 mV (VIT+ = 50 mV, VIT− = −50 mV) with open-circuit fail-safe."+ },+ {+ "number": "2",+ "name": "1A",+ "type": "input",+ "description": "Non-inverting (A) differential input of receiver 1, which detects a 50 mV differential input with up to 1 V ground potential difference between transmitter and receiver."+ },+ {+ "number": "3",+ "name": "1R",+ "type": "output",+ "description": "LVTTL output of receiver 1 that is high impedance when RE is high, with VOH of at least 2.4 V at −8 mA and VOL of at most 0.4 V at 8 mA."+ },+ {+ "number": "4",+ "name": "RE",+ "type": "input",+ "description": "Active-low receiver enable shared by both receivers; a high level places the R outputs in high impedance, with VIH of at least 2 V and VIL of at most 0.8 V."+ },+ {+ "number": "5",+ "name": "2R",+ "type": "output",+ "description": "LVTTL output of receiver 2 that is high impedance when RE is high, with VOH of at least 2.4 V at −8 mA and VOL of at most 0.4 V at 8 mA."+ },+ {+ "number": "6",+ "name": "2A",+ "type": "input",+ "description": "Non-inverting (A) differential input of receiver 2, which detects a 50 mV differential input with up to 1 V ground potential difference between transmitter and receiver."+ },+ {+ "number": "7",+ "name": "2B",+ "type": "input",+ "description": "Inverting (B) differential input of receiver 2, which resolves a differential input of ±50 mV (VIT+ = 50 mV, VIT− = −50 mV) with open-circuit fail-safe."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground; all voltages except differential I/O bus voltages are referenced to this network ground terminal."+ },+ {+ "number": "9",+ "name": "2D",+ "type": "input",+ "description": "Driver 2 LVTTL data input, 5 V tolerant, with VIH of at least 2 V and VIL of at most 0.8 V."+ },+ {+ "number": "10",+ "name": "2Y",+ "type": "output",+ "description": "Non-inverting LVDS output of driver 2, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V."+ },+ {+ "number": "11",+ "name": "2Z",+ "type": "output",+ "description": "Inverting LVDS output of driver 2, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V."+ },+ {+ "number": "12",+ "name": "DE",+ "type": "input",+ "description": "Active-high driver enable shared by both drivers; a low level forces Y and Z of both drivers to high impedance, with VIH of at least 2 V and VIL of at most 0.8 V."+ },+ {+ "number": "13",+ "name": "1Z",+ "type": "output",+ "description": "Inverting LVDS output of driver 1, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V."+ },+ {+ "number": "14",+ "name": "1Y",+ "type": "output",+ "description": "Non-inverting LVDS output of driver 1, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V."+ },+ {+ "number": "15",+ "name": "1D",+ "type": "input",+ "description": "Driver 1 LVTTL data input, 5 V tolerant, with VIH of at least 2 V and VIL of at most 0.8 V."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Single supply pin, specified from 3 V to 3.6 V with 3.3 V nominal."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The MPN SN65LVDM050QDG4Q1 is listed in the addendum (page 18) as SOIC (D), 16 pins, with part markin; The pin-to-number mapping was reconstructed from the text-extracted diagram labels on page 1, matchi; The 051 diagram on the same page (1DE/2DE, no RE) was not used, since it does not apply to this MPN."+ ],+ "pages_sent": 24,+ "cost_usd": 0.0971,+ "at": "2026-10-08T14:39:25"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn65lvdm051-q1",+ "pages": 24,+ "sha256": "bbb259bd55ba22b0",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn65lvdm050qdg4q1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn65lvdm050qdg4q1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "0ca72a1641eb88026c94b98fe85eb5f558bf8e12e2bee02003e4d235c64001b2",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}