# SN65LVDM050PWR

**Texas Instruments** · LVDS ICs · TSSOP-16

SN65LVDM050PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1B | input | Channel 1 differential receiver input B, which detects a differential input voltage of 50 mV. |
| 2 | 1A | input | Channel 1 differential receiver input A, which detects a differential input voltage of 50 mV. |
| 3 | 1R | output | Channel 1 receiver data output, driven high for VID ≥ 50 mV and low for VID ≤ -50 mV. |
| 4 | RE | input | Receiver enable input, LVTTL level and 5-V tolerant. |
| 5 | 2R | output | Channel 2 receiver data output, driven high for VID ≥ 50 mV and low for VID ≤ -50 mV. |
| 6 | 2A | input | Channel 2 differential receiver input A, which detects a differential input voltage of 50 mV. |
| 7 | 2B | input | Channel 2 differential receiver input B, which detects a differential input voltage of 50 mV. |
| 8 | GND | power_in | Ground. |
| 9 | 2D | input | Channel 2 driver data input, LVTTL level and 5-V tolerant. |
| 10 | 2Y | output | Channel 2 non-inverting LVDS driver output, with a typical output voltage of 340 mV into a 50-Ω load. |
| 11 | 2Z | output | Channel 2 inverting LVDS driver output, with a typical output voltage of 340 mV into a 50-Ω load. |
| 12 | DE | input | Driver enable input, LVTTL level and 5-V tolerant; the driver is high impedance when disabled. |
| 13 | 1Z | output | Channel 1 inverting LVDS driver output, with a typical output voltage of 340 mV into a 50-Ω load. |
| 14 | 1Y | output | Channel 1 non-inverting LVDS driver output, with a typical output voltage of 340 mV into a 50-Ω load. |
| 15 | 1D | input | Channel 1 driver data input, LVTTL level and 5-V tolerant. |
| 16 | VCC | power_in | Single 3.3-V supply; the driver outputs are high impedance when VCC < 1.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `SN65LVDM050PWR`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `sn65lvdm050pwr-etched.step` / `sn65lvdm050pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn65lvdm050pwr.step` / `sn65lvdm050pwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn65lvdm050.pdf) (41 pp, sha256 `37c047cec245475d`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn65lvdm050pwr-datasheet.pdf)