component
SN65LVCP202RGER
Public Made by Adomby adom
Texas Instruments Signal Switches, Multiplexers, Decoders, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
SN65LVCP202RGER
Texas Instruments · Signal Switches, Multiplexers, Decoders · VQFN-24-EP(4x4)
SN65LVCP202RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | input | Channel 1 switching select (LVTTL): S1 = 0 routes 1A/1B to output channel 1 and S1 = 1 routes 2A/2B to it. |
| 2 | 1A | input | Line-side differential input, positive leg (xA = P), CML compatible, with 50-Ω termination to VBB. |
| 3 | 1B | input | Line-side differential input, negative leg (xB = N), CML compatible, with 50-Ω termination to VBB. |
| 4 | VBB | input | Receiver input biasing voltage; the datasheet gives an open-circuit input self-bias voltage of 1.6 V for AC-coupled inputs. |
| 5 | 2A | input | Line-side differential input, positive leg (xA = P), CML compatible, with 50-Ω termination to VBB. |
| 6 | 2B | input | Line-side differential input, negative leg (xB = N), CML compatible, with 50-Ω termination to VBB. |
| 7 | 2DE | input | Channel 2 data enable, active-low LVTTL; when not enabled, output 2Y/2Z is in high-impedance state for power savings. |
| 8 | VCC | power_in | Power supply, 3.3 V ±5% (3.135 V to 3.465 V recommended). |
| 9 | P21 | input | Channel 2 output preemphasis control bit (LVTTL), used with P22 to set 0, 3, 6 or 9 dB preemphasis on output channel 2. |
| 10 | P22 | input | Channel 2 output preemphasis control bit (LVTTL), used with P21 to set 0, 3, 6 or 9 dB preemphasis on output channel 2. |
| 11 | GND | power_in | Ground. |
| 12 | VCC | power_in | Power supply, 3.3 V ±5% (3.135 V to 3.465 V recommended). |
| 13 | 2Z | output | Switch-side differential output, negative leg (xZ = N), VML signaling, with 100-Ω differential load expected (80 to 120 Ω). |
| 14 | 2Y | output | Switch-side differential output, positive leg (xY = P), VML signaling, with 100-Ω differential load expected (80 to 120 Ω). |
| 15 | GND | power_in | Ground. |
| 16 | 1Z | output | Switch-side differential output, negative leg (xZ = N), VML signaling, with 100-Ω differential load expected (80 to 120 Ω). |
| 17 | 1Y | output | Switch-side differential output, positive leg (xY = P), VML signaling, with 100-Ω differential load expected (80 to 120 Ω). |
| 18 | S2 | input | Channel 2 switching select (LVTTL): S2 = 0 routes 1A/1B to output channel 2 and S2 = 1 routes 2A/2B to it. |
| 19 | VCC | power_in | Power supply, 3.3 V ±5% (3.135 V to 3.465 V recommended). |
| 20 | GND | power_in | Ground. |
| 21 | P12 | input | Channel 1 output preemphasis control bit (LVTTL), used with P11 to set 0, 3, 6 or 9 dB preemphasis on output channel 1. |
| 22 | P11 | input | Channel 1 output preemphasis control bit (LVTTL), used with P12 to set 0, 3, 6 or 9 dB preemphasis on output channel 1. |
| 23 | EQ | input | Receive equalization select: EQ = 1 (default) selects 5 dB equalization and EQ = 0 selects 12 dB equalization. |
| 24 | 1DE | input | Channel 1 data enable, active-low LVTTL; when not enabled, output 1Y/1Z is in high-impedance state for power savings. |
| 25 | GND | power_in | Exposed center thermal pad must be connected to the GND plane with thermal vias and soldered to the PCB for thermal and mechanical performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Logic |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
SN65LVCP202RGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
sn65lvcp202rger-etched.step/sn65lvcp202rger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn65lvcp202rger.step/sn65lvcp202rger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
a1ab93ef9773f0a9, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN65LVCP202RGER
**Texas Instruments** · Signal Switches, Multiplexers, Decoders · VQFN-24-EP(4x4)
SN65LVCP202RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | input | Channel 1 switching select (LVTTL): S1 = 0 routes 1A/1B to output channel 1 and S1 = 1 routes 2A/2B to it. |
| 2 | 1A | input | Line-side differential input, positive leg (xA = P), CML compatible, with 50-Ω termination to VBB. |
| 3 | 1B | input | Line-side differential input, negative leg (xB = N), CML compatible, with 50-Ω termination to VBB. |
| 4 | VBB | input | Receiver input biasing voltage; the datasheet gives an open-circuit input self-bias voltage of 1.6 V for AC-coupled inputs. |
| 5 | 2A | input | Line-side differential input, positive leg (xA = P), CML compatible, with 50-Ω termination to VBB. |
| 6 | 2B | input | Line-side differential input, negative leg (xB = N), CML compatible, with 50-Ω termination to VBB. |
| 7 | 2DE | input | Channel 2 data enable, active-low LVTTL; when not enabled, output 2Y/2Z is in high-impedance state for power savings. |
| 8 | VCC | power_in | Power supply, 3.3 V ±5% (3.135 V to 3.465 V recommended). |
| 9 | P21 | input | Channel 2 output preemphasis control bit (LVTTL), used with P22 to set 0, 3, 6 or 9 dB preemphasis on output channel 2. |
| 10 | P22 | input | Channel 2 output preemphasis control bit (LVTTL), used with P21 to set 0, 3, 6 or 9 dB preemphasis on output channel 2. |
| 11 | GND | power_in | Ground. |
| 12 | VCC | power_in | Power supply, 3.3 V ±5% (3.135 V to 3.465 V recommended). |
| 13 | 2Z | output | Switch-side differential output, negative leg (xZ = N), VML signaling, with 100-Ω differential load expected (80 to 120 Ω). |
| 14 | 2Y | output | Switch-side differential output, positive leg (xY = P), VML signaling, with 100-Ω differential load expected (80 to 120 Ω). |
| 15 | GND | power_in | Ground. |
| 16 | 1Z | output | Switch-side differential output, negative leg (xZ = N), VML signaling, with 100-Ω differential load expected (80 to 120 Ω). |
| 17 | 1Y | output | Switch-side differential output, positive leg (xY = P), VML signaling, with 100-Ω differential load expected (80 to 120 Ω). |
| 18 | S2 | input | Channel 2 switching select (LVTTL): S2 = 0 routes 1A/1B to output channel 2 and S2 = 1 routes 2A/2B to it. |
| 19 | VCC | power_in | Power supply, 3.3 V ±5% (3.135 V to 3.465 V recommended). |
| 20 | GND | power_in | Ground. |
| 21 | P12 | input | Channel 1 output preemphasis control bit (LVTTL), used with P11 to set 0, 3, 6 or 9 dB preemphasis on output channel 1. |
| 22 | P11 | input | Channel 1 output preemphasis control bit (LVTTL), used with P12 to set 0, 3, 6 or 9 dB preemphasis on output channel 1. |
| 23 | EQ | input | Receive equalization select: EQ = 1 (default) selects 5 dB equalization and EQ = 0 selects 12 dB equalization. |
| 24 | 1DE | input | Channel 1 data enable, active-low LVTTL; when not enabled, output 1Y/1Z is in high-impedance state for power savings. |
| 25 | GND | power_in | Exposed center thermal pad must be connected to the GND plane with thermal vias and soldered to the PCB for thermal and mechanical performance. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Logic |
| Pins | 25 |
## CAD (KiCad official)
- Symbol: `SN65LVCP202RGER`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`
- 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `sn65lvcp202rger-etched.step` / `sn65lvcp202rger-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn65lvcp202rger.step` / `sn65lvcp202rger.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn65lvcp202) (21 pp, sha256 `a1ab93ef9773f0a9`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn65lvcp202rger-datasheet.pdf)