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README

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SN65HVS883PWPR

Texas Instruments · Global Sourcing Parts · HTSSOP-28-EP

SN65HVS883PWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DB0 input Debounce-select logic input; together with DB1 it selects 3 ms, 1 ms, or 0 ms (filter bypassed) input debounce, is internally pulled high, and has an absolute maximum of 6 V.
2 DB1 input Debounce-select logic input; together with DB0 it selects the debounce time, is internally pulled high, and has an absolute maximum of 6 V.
3 IP0 input Field digital input channel 0, which acts as a controlled current sink limited to about 3.6 mA by RLIM and accepts field voltages up to 34 V (absolute maximum 36 V).
4 RE0 output Return path for channel 0 LED drive, sinking 2.8 mA to 3.5 mA when RLIM = 25 kΩ and the pin is tied to FGND.
5 IP1 input Field digital input channel 1, which acts as a controlled current sink limited to about 3.6 mA by RLIM and accepts field voltages up to 34 V (absolute maximum 36 V).
6 RE1 output Return path for channel 1 LED drive, sinking 2.8 mA to 3.5 mA when RLIM = 25 kΩ and the pin is tied to FGND.
7 IP2 input Field digital input channel 2, which acts as a controlled current sink limited to about 3.6 mA by RLIM and accepts field voltages up to 34 V (absolute maximum 36 V).
8 RE2 output Return path for channel 2 LED drive, sinking 2.8 mA to 3.5 mA when RLIM = 25 kΩ and the pin is tied to FGND.
9 IP3 input Field digital input channel 3, which acts as a controlled current sink limited to about 3.6 mA by RLIM and accepts field voltages up to 34 V (absolute maximum 36 V).
10 RE3 output Return path for channel 3 LED drive, sinking 2.8 mA to 3.5 mA when RLIM = 25 kΩ and the pin is tied to FGND.
11 IP4 input Field digital input channel 4, which acts as a controlled current sink limited to about 3.6 mA by RLIM and accepts field voltages up to 34 V (absolute maximum 36 V).
12 RE4 output Return path for channel 4 LED drive, sinking 2.8 mA to 3.5 mA when RLIM = 25 kΩ and the pin is tied to FGND.
13 RLIM passive Current-limit setting resistor connection to FGND, where ILIM = 90 V / RLIM and RLIM must be between 17 kΩ and 500 kΩ (25 kΩ gives 3.6 mA).
14 V24 power_in 24 VDC field supply input, specified for 10 V to 34 V with an absolute maximum of 36 V.
15 5VOP power_out 5 V regulator output for supplying low-power digital isolators, rated for 50 mA with a 115 mA typical current limit and 4.5 V to 5.5 V output.
16 CHOK output Chip-okay indicator output that goes low about 1 ms after V24 falls below 15 V and returns high 6 ms after supply recovery, with output current limited to ±8 mA.
17 RE5 output Return path for channel 5 LED drive, sinking 2.8 mA to 3.5 mA when RLIM = 25 kΩ and the pin is tied to FGND.
18 IP5 input Field digital input channel 5, which acts as a controlled current sink limited to about 3.6 mA by RLIM and accepts field voltages up to 34 V (absolute maximum 36 V).
19 RE6 output Return path for channel 6 LED drive, sinking 2.8 mA to 3.5 mA when RLIM = 25 kΩ and the pin is tied to FGND.
20 IP6 input Field digital input channel 6, which acts as a controlled current sink limited to about 3.6 mA by RLIM and accepts field voltages up to 34 V (absolute maximum 36 V).
21 RE7 output Return path for channel 7 LED drive, sinking 2.8 mA to 3.5 mA when RLIM = 25 kΩ and the pin is tied to FGND.
22 IP7 input Field digital input channel 7, which acts as a controlled current sink limited to about 3.6 mA by RLIM and accepts field voltages up to 34 V (absolute maximum 36 V).
23 SOP output Serial data output of the shift register, which can be daisy-chained to the SIP input of the next device, with output current limited to ±8 mA.
24 CE input Clock-enable input where a low enables serial shifting and a high inhibits it, and which should only transition low while CLK is low; absolute maximum 6 V.
25 CLK input Serial clock input where data shifts in on the rising edge and out on the falling edge, with a clock frequency up to 100 MHz and an absolute maximum of 6 V.
26 LD input Load pulse input where a low level loads the field inputs in parallel and a high level switches the device to shift mode; absolute maximum 6 V.
27 SIP input Serial data input, internally pulled high, which appears at SOP after eight clock cycles; absolute maximum 6 V.
28 FGND power_in Field ground, which is the reference for all field-side voltages and is the connection for the RE return paths and RLIM.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-28-EP
Category Global Sourcing Parts
Pins 29

CAD (KiCad official)

  • Symbol: SN65HVS883PWPR
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
  • 3D model files: sn65hvs883pwpr-etched.step / sn65hvs883pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65hvs883pwpr.step / sn65hvs883pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 a0acf15735bf2bdd, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF