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SN65HVD64RGTR

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Texas Instruments RS-485/RS-422 ICs, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN65HVD64RGTR

Texas Instruments · RS-485/RS-422 ICs · VQFN-16-EP(3x3)

SN65HVD64RGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNCOUT output Open-drain output that synchronizes other devices to the 4x-carrier oscillator at XTAL1 and XTAL2, used with a 1-kΩ pullup resistor to VCC.
2 TXIN input Digital data bit stream input to the driver, with a high-level input of 70% VL minimum and a low-level input of 30% VL maximum.
3 VL power_in Logic supply voltage for the device, specified from 1.6 V to 5.5 V.
4 RXOUT output Digital data bit stream output from the receiver.
5 DIR output Direction control output signal for RS-485 bus arbitration, with its duration set by DIRSET1 and DIRSET2.
6 DIRSET2 input Together with DIRSET1 sets the DIR duration: L:L is 9.6 kbps, L:H is 38.4 kbps, H:L is 115 kbps, and H:H is standby mode, with input levels of 70% VL minimum for high and 30% VL maximum for low.
7 DIRSET1 input Together with DIRSET2 sets the DIR duration: L:L is 9.6 kbps, L:H is 38.4 kbps, H:L is 115 kbps, and H:H is standby mode, with input levels of 70% VL minimum for high and 30% VL maximum for low.
8 GND power_in Ground connection for the device.
9 RES input Input voltage that adjusts driver output power, set by external resistors from BIAS to RES and RES to GND, with VRES limited to 0.7 V to 1.5 V.
10 BIAS output Bias voltage output for setting driver output power through external resistors, with R1 of 4.1 kΩ between BIAS and RES and a 1-µF capacitor to GND.
11 RXIN input Modulated input signal to the receiver, with an input amplitude of 1.12 Vpp at RXIN.
12 TXOUT output Modulated output signal from the driver, loaded with 50 Ω between TXOUT and RXIN.
13 VCC power_in Analog supply voltage for the device, specified from 3 V to 5.5 V.
14 XTAL1 bidirectional Crystal oscillator I/O pin; connect a 4 × fC crystal between XTAL1 and XTAL2, or drive XTAL1 with an 8.704-MHz clock while XTAL2 is connected to GND.
15 XTAL2 bidirectional Crystal oscillator I/O pin; connect a 4 × fC crystal between XTAL1 and XTAL2, or connect XTAL2 to GND when XTAL1 is driven by an 8.704-MHz clock.
16 GND power_in Ground connection for the device.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category Communication Interface Chip/UART/485/232
Pins 17

CAD (KiCad official)

  • Symbol: SN65HVD64RGTR
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: sn65hvd64rgtr-etched.step / sn65hvd64rgtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65hvd64rgtr.step / sn65hvd64rgtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 69d4256f4a9003ca, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF