SN65HVD63RGTR from Texas Instruments, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SYNCOUT	output	Open-drain output used to synchronize other devices to the 4x-carrier oscillator at XTAL1 and XTAL2, requiring a pullup of at least 1 kΩ to VCC.
2	TXIN	input	Digital data bit stream input to the driver, with logic-high input voltage of at least 70% VL and logic-low at most 30% VL.
3	VL	power_in	Logic supply voltage for the device, specified from 1.6 V to 5.5 V.
4	RXOUT	output	Digital data bit stream output from the receiver.
5	DIR	output	Direction control output signal for RS-485 bus arbitration, with its duration set by DIRSET1 and DIRSET2.
6	DIRSET2	input	Bit that sets the DIR duration together with DIRSET1: [L:L] = 9.6 kbps, [L:H] = 38.4 kbps, [H:L] = 115 kbps, [H:H] = standby mode.
7	DIRSET1	input	Bit that sets the DIR duration together with DIRSET2, with logic-high input voltage of at least 70% VL and logic-low at most 30% VL.
8	GND	power_in	Ground connection for the device.
9	RES	input	Input voltage that adjusts driver output power, set by external resistors from BIAS to GND, with a specified range of 0.7 V to 1.5 V.
10	BIAS	output	Bias voltage output for setting driver output power through external resistors, requiring 1 µF capacitance to GND.
11	RXIN	input	Modulated input signal to the receiver, with a maximum amplitude of 1.12 Vpp.
12	TXOUT	output	Modulated output signal from the driver, delivering 0 dBm to 6 dBm into a 50-Ω load.
13	VCC	power_in	Analog supply voltage for the device, specified from 3 V to 5.5 V.
14	XTAL1	bidirectional	I/O pin of the crystal oscillator; connect a 4 × fC crystal between XTAL1 and XTAL2, or connect XTAL1 to an 8.704-MHz clock with XTAL2 tied to GND.
15	XTAL2	bidirectional	I/O pin of the crystal oscillator; connect a 4 × fC crystal between XTAL1 and XTAL2, or tie XTAL2 to GND when XTAL1 is driven by an 8.704-MHz clock.
16	GND	power_in	Ground connection for the device.
17	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	QFN-16-EP(3x3)
Category	Interface ICs
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage, VCC and VL	VCC, VL	-0.5		6	V		4
Voltage at coax pins		-0.5		6	V		4
Voltage at logic pins		-0.3			V	maximum printed as VVL + 0.3	4
Logic output current		-20		20	mA		4
Junction temperature	TJ			170	°C		4
Storage temperature	Tstg	-65		150	°C		4
Analog supply voltage	VCC	3		5.5	V		4
Logic supply voltage	VL	1.6		5.5	V		4
Input signal amplitude at RXIN	VI(pp)			1.12	Vpp		4
High-level input voltage (TXIN, DIRSET1, DIRSET2)	VIH	70			%VL	maximum printed as VL	4
High-level input voltage (XTAL1, XTAL2)	VIH	70			%VCC	maximum printed as VCC	4
Low-level input voltage (TXIN, DIRSET1, DIRSET2)	VIL	0		30	%VL		4
Low-level input voltage (XTAL1, XTAL2)	VIL	0		30	%VCC		4
Data signaling rate	1/tUI	9.6		115	kbps		4
Oscillator frequency tolerance	FOSC	-30		30	ppm	nominal 8.704 MHz	4
Voltage at RES pin	VRES	0.7		1.5	V		4
Operating free-air temperature	TA	-40		105	°C		4
Junction temperature (operating)	TJ	-40		125	°C		4
Supply current, TXIN = L (active)	ICC		28	33	mA	DIRSET1 = L, DIRSET2 = H; TXIN = L (active)	6
Supply current, TXIN = H (quiescent)	ICC		25	31	mA	DIRSET1 = L, DIRSET2 = H; TXIN = H (quiescent)	6
Supply current, TXIN = 115 kbps	ICC		27	33	mA	TXIN = 115 kbps, 50% duty cycle	6
Supply current, standby	ICC		12	17	mA	DIRSET1 = H, DIRSET2 = H (standby)	6
Logic supply current	IVL			50	µA	TXIN = H, RXIN = DC input	6
Receiver power supply rejection ratio	PSRR	45		60	dB	VTXIN = VL	6
High-level logic output voltage (RXOUT, DIR)	VOH	90			%VL	IOH = -4 mA for VL > 2.4 V; IOH = -2 mA for VL < 2.4 V	6
Low-level logic output voltage (RXOUT, DIR)	VOL			10	%VL	IOL = 4 mA for VL > 2.4 V; IOL = 2 mA for VL < 2.4 V	6
Peak-to-peak output voltage at device pin TXOUT	VO(PP)	2.24		2.5	VPP	VRES = 1.5 V (Maximum setting)	6
Peak-to-peak output voltage at device pin TXOUT	VO(PP)	1.17		1.3	VPP	VRES = 0.7 V (Minimum setting)	6
Peak-to-peak voltage at coax out	VO(PP)	5		6	dBm	VRES = 1.5 V	6
Peak-to-peak voltage at coax out	VO(PP)	-0.6		0.3	dBm	VRES = 0.7 V	6
Off-state output voltage	VO(OFF)			1	mVpp	At TXOUT	6
Output frequency variation	Δf	-100		100	ppm		6
Short-circuit output current	IOS	300		450	mA	TXOUT short-circuit	6
Input threshold	VIT	79	112	158	mVPP	fIN = 2.176 MHz	6
Input impedance	ZIN	11		21	kΩ	f = fO	6
Passband	fPB	1.1		4.17	MHz	VRXIN = 1.12VP_P	6
Receiver rejection range	fREJ	1.1		4.17	MHz	2.176-MHz carrier amplitude of 112.4 mVPP, frequency band of spurious components with 800 mVPP allowed	6
Input leakage current	II	-15		15	µA	XTAL1, XTAL2, 0V < VIN < VCC	6
Output low voltage SYNCOUT	VOL			0.4	V	with 1-kΩ resistor from SYNCOUT to VCC	6
Coax driver propagation delay	tpAQ, tpQA			5	µs	See Figure 19	7
Coax receiver output rise/fall time	tr, tf			20	ns	CL = 15 pF, RL = 1 kΩ; see Figure 19	7
Receiver propagation delay	tPHL, tPLH		5.5	11	µs	See Figure 20	7
Coax receiver output duty cycle		40		60	%	VRXIN(ON) = 630 mVpp, VRXIN(OFF) < 5 mVpp, 50% duty cycle	7
Direction control skew (DIR to RXOUT)	tDIRSKEW			270	ns	DIR to RXOUT	7
Transmitter output impedance	ZO		0.03		Ω	At 100 kHz	6
Output frequency	fO		2.176		MHz		6
Direction control active duration	tDIR		1667		µs	DIRSET2 = GND or OPEN, DIRSET1 = GND or OPEN	7
Direction control active duration	tDIR		417		µs	DIRSET2 = GND, DIRSET1 = VL	7
Direction control active duration	tDIR		137		µs	DIRSET2 = VL, DIRSET1 = VL	7
Receiver noise filter time (slow bit rate)	tnoise filter		4		µs	DIRSET for 9.6 kbps	6
Receiver noise filter time (fast bit rate)	tnoise filter		2		µs	DIRSET for > 9.6 kbps	6
Bias resistor between BIAS and RES	R1		4.1		kΩ		4
Bias resistor between RES and GND	R2		10		kΩ		4
Pullup resistor between SYNCOUT and VCC	RSYNC		1		kΩ		4
Coupling capacitance between RXIN and coax (channel)	CC		220		nF		4
Capacitance between BIAS and GND	CBIAS		1		µF		4
Load impedance between RXIN and GND at fC (channel)	ZLOAD		50		Ω		4
Junction-to-ambient thermal resistance	RθJA		49.4		°C/W		4
Junction-to-case (top) thermal resistance	RθJCtop		64.2		°C/W		5
Junction-to-board thermal resistance	RθJB		22.9		°C/W		5
Junction-to-case (bottom) thermal resistance	RθJCbot		25		°C/W		5

CAD (KiCad official)

Symbol: SN65HVD63RGTR
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
3D model files: sn65hvd63rgtr-etched.step / sn65hvd63rgtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65hvd63rgtr.step / sn65hvd63rgtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (28 pp, sha256 4ca34813818bf3d8, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

SN65HVD63RGTR

Verified SN65HVD63RGTR

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3D Model

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