# SN65HVD61DR

**Texas Instruments** · Interface - Specialized · SOIC-14

SN65HVD61DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RX | output | Primary receiver output, high when VXF3 exceeds VXF1 by more than VTH+ and low below VTH-, high-impedance when CHEN is low; rated ±15 mA absolute max, 8 mA recommended. |
| 2 | CD | output | Carrier detect output, high when (VXF3 - VXF1) exceeds VCD (175 to 255 mV) and low otherwise, high-impedance when CHEN is low; rated ±15 mA absolute max. |
| 3 | VDD | power_in | I/O supply voltage of 2.375 V to 5.5 V (absolute max 6 V), should match the controller supply. |
| 4 | CHEN | input | Chip enable logic input; low or open disables the chip (low-power standby, RX and CD high-impedance), high enables it; input range -0.5 to 6 V. |
| 5 | TX | input | Transmitter logic input; with TXBAR low or open and TXEN high it drives XF3 low, input range -0.5 to 6 V. |
| 6 | TXBAR | input | Complementary transmitter logic input (active-low TX); TX and TXBAR both high is not supported in ControlNet applications, input range -0.5 to 6 V. |
| 7 | TXEN | input | Transmitter enable logic input; low or open places XF1 and XF3 in high-impedance state, input range -0.5 to 6 V. |
| 8 | SIG | output | Signal strength analog output proportional to the differential voltage between XF1 and XF3 (1.25 V typ at zero input, gain 120 to 140 mV/V), for diagnostics; output current ±1 mA. |
| 9 | DGND | power_in | Digital ground, to be connected to a common ground plane with CGND external to the device. |
| 10 | XF3 | bidirectional | Bus terminal to the transformer, transmitter sink output and receiver input, voltage range -22 to +22 V absolute max, current internally limited. |
| 11 | CGND | power_in | Analog (bus) ground, tied internally to pin 13 and to be connected to a common ground plane with DGND. |
| 12 | XF1 | bidirectional | Bus terminal to the transformer, transmitter sink output and receiver input, voltage range -22 to +22 V absolute max, current internally limited. |
| 13 | CGND | power_in | Analog (bus) ground, second CGND pin shown with pin 11 in the functional diagram. |
| 14 | VCC | power_in | Analog supply voltage of 4.5 V to 5.5 V (5 V nominal, absolute max 6 V); device is disabled below 2.1 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Interface |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `SN65HVD61DR`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `sn65hvd61dr-etched.step` / `sn65hvd61dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn65hvd61dr.step` / `sn65hvd61dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn65hvd61.pdf) (22 pp, sha256 `942e32f8c7d3d5a3`, retrieved 2026-10-08, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn65hvd61dr-datasheet.pdf)