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SN65HVD35DR

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Texas Instruments RS-485/RS-422 ICs, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN65HVD35DR

Texas Instruments · RS-485/RS-422 ICs · SOIC-14

SN65HVD35DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection; must be left floating.
2 R output Receive data output.
3 RE input Receiver enable, active low.
4 DE input Driver enable, active high.
5 D input Driver data input.
6 GND power_in Local device ground; internally connected to pin 7.
7 GND power_in Local device ground; internally connected to pin 6.
8 NC unconnected No internal connection; must be left floating.
9 Y output Driver output (complementary to Z).
10 Z output Driver output (complementary to Y).
11 B input Receiver input (complementary to A).
12 A input Receiver input (complementary to B).
13 VCC power_in 3-V to 3.6-V supply; internally connected to pin 14.
14 VCC power_in 3-V to 3.6-V supply; internally connected to pin 13.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Interface ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.3 6 V 7
Voltage at any bus terminal V(A), V(B), V(Y), V(Z) -9 14 V 7
Transient pulse voltage V(TRANS) -50 50 V through 100 Ω, Figure 8-13 7
Input voltage (D, DE, RE) VI -0.5 7 V 7
Output current (receiver output R) IO 11 mA 7
HBM ESD, bus pins and GND V(ESD) -16000 16000 V HBM per ANSI/ESDA/JEDEC JS-001 7
HBM ESD, all pins V(ESD) -4000 4000 V HBM per ANSI/ESDA/JEDEC JS-001 7
CDM ESD V(ESD) -1000 1000 V CDM per JESD22-C101 7
Supply voltage VCC 3 3.6 V 8
Voltage at any bus pin VI or VIC -7 12 V separately or common mode 8
Signaling rate 1/tUI 1 Mbps SN65HVD32, SN65HVD35 8
Differential load resistance RL 54 60 Ω 8
High-level input voltage VIH 2 V D, DE, RE; max VCC 8
Low-level input voltage VIL 0 0.8 V D, DE, RE 8
Differential input voltage VID -12 12 V 8
High-level output current, driver IOH -60 mA Driver 8
High-level output current, receiver IOH -8 mA Receiver 8
Low-level output current, driver IOL 60 mA Driver 8
Low-level output current, receiver IOL 8 mA Receiver 8
Junction temperature TJ -40 150 °C 8
Junction-to-ambient thermal resistance RθJA 93.2 °C/W D (SOIC) 14 pins 8
Junction-to-case (top) thermal resistance RθJC(top) 47.5 °C/W D (SOIC) 14 pins 8
Junction-to-board thermal resistance RθJB 49.4 °C/W D (SOIC) 14 pins 8
Junction-to-top characterization parameter ψJT 11.2 °C/W D (SOIC) 14 pins 8
Junction-to-board characterization parameter ψJB 48.9 °C/W D (SOIC) 14 pins 8
Driver input clamp voltage VI(K) -1.5 V II = -18 mA 9
Steady-state differential output voltage /VOD(SS)/ 2.5 V IO = 0 9
Steady-state differential output voltage /VOD(SS)/ 1.5 2 V RL = 54 Ω, See Figure 8-2 (RS-485) 9
Steady-state differential output voltage /VOD(SS)/ 2 2.3 V RL = 100 Ω, See Figure 8-2 (RS-422) 9
Steady-state differential output voltage /VOD(SS)/ 1.5 V Vtest = -7 V to 12 V, See Figure 8-3 9
Change in magnitude of steady-state differential output voltage Δ/VOD(SS)/ -0.2 0.2 V RL = 54 Ω, See Figure 8-2 and Figure 8-3 9
Differential output voltage overshoot and undershoot VOD(RING) 10 V RL = 54 Ω, CL = 50 pF; 10% of peak-to-peak differential swing (unit %) 9
Peak-to-peak common-mode output voltage VOC(PP) 0.25 V See Figure 8-5 9
Steady-state common-mode output voltage VOC(SS) 1.6 2.3 V See Figure 8-5 9
Change in steady-state common-mode output voltage ΔVOC(SS) -0.05 0.05 V See Figure 8-5 9
High-impedance state output current IZ(Z) or IY(Z) 90 μA VCC = 3 V or 0 V, DE = 0 V, VZ or VY = 12 V, other input at 0 V 9
High-impedance state output current IZ(Z) or IY(Z) -10 μA VCC = 3 V or 0 V, DE = 0 V, VZ or VY = -7 V, other input at 0 V 9
Short circuit output current IZ(S) or IY(S) -250 250 mA VZ or VY = -7 V, other input at 0 V 9
Input current D, DE II 0 100 μA 9
Differential output capacitance C(OD) 16 pF VOD = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 9
Positive-going differential input threshold voltage VIT+ -0.02 V IO = -8 mA 10
Negative-going differential input threshold voltage VIT- -0.2 V IO = 8 mA 10
Hysteresis voltage (VIT+, VIT-) Vhys 50 mV 10
Enable-input clamp voltage VIK -1.5 V II = -18 mA 10
Receiver output voltage high VO 2.4 V VID = 200 mV, IO = -8 mA, See Figure 8-9 10
Receiver output voltage low VO 0.4 V VID = -200 mV, IO = 8 mA, See Figure 8-9 10
High-impedance-state output current IO(Z) -1 1 μA VO = 0 or VCC, RE at VCC 10
Bus input current IA or IB 0.05 0.1 mA VA or VB = 12 V, other input at 0 V 10
Bus input current IA or IB 0.06 0.1 mA VA or VB = 12 V, VCC = 0 V, other input at 0 V 10
Bus input current IA or IB -0.1 -0.04 mA VA or VB = -7 V, other input at 0 V 10
Bus input current IA or IB -0.1 -0.03 mA VA or VB = -7 V, VCC = 0 V, other input at 0 V 10
Differential input capacitance CID 15 pF VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 10
Power dissipation (worst case) PD 248 mW SN65HVD35 at 1 Mbps, VCC = 3.6 V, TJ = 140°C, RL = 54 Ω, CL = 50 pF (driver), CL = 15 pF (receiver) 10
Thermal shut-down junction temperature TSD 170 °C 10
Supply current, standby ICC 0.022 1 μA RE at VCC, D at VCC, DE at 0 V, No load (receiver and driver disabled) 11
Supply current, receiver enabled driver disabled ICC 2.2 mA RE at 0 V, D at 0 V or VCC, DE at 0 V, No load 11
Supply current, receiver and driver enabled ICC 6.5 mA RE at 0 V, D at 0 V or VCC, DE at VCC, No load 11
Supply current, receiver disabled driver enabled ICC 6.2 mA RE at VCC, D at 0 V or VCC, DE at VCC, No load 11
Driver propagation delay, low-to-high tPLH 120 175 305 ns RL = 54 Ω, CL = 50 pF, See Figure 8-6 11
Driver propagation delay, high-to-low tPHL 120 175 305 ns RL = 54 Ω, CL = 50 pF, See Figure 8-6 11
Driver differential output rise time tr 120 185 300 ns RL = 54 Ω, CL = 50 pF, See Figure 8-6 11
Driver differential output fall time tf 120 180 300 ns RL = 54 Ω, CL = 50 pF, See Figure 8-6 11
Driver pulse skew tsk(p) 5.1 ns /tPHL, tPLH/ 11
Driver enable time, high-impedance-to-high tPZH1 490 ns RL = 110 Ω, RE at 0 V, See Figure 8-7 12
Driver disable time, high-to-high-impedance tPHZ 165 ns RL = 110 Ω, RE at 0 V, See Figure 8-7 12
Driver enable time, high-impedance-to-low tPZL1 490 ns RL = 110 Ω, RE at 0 V, See Figure 8-8 12
Driver disable time, low-to-high-impedance tPLZ 290 ns RL = 110 Ω, RE at 0 V, See Figure 8-8 12
Driver enable delay with bus voltage offset tPZH1, tPZL1 500 900 ns VO = 2 V (Typ) 12
Driver standby-to-high-level delay tPZH2 4000 ns RL = 110 Ω, RE at 3 V, See Figure 8-7 12
Driver standby-to-low-level delay tPZL2 4000 ns RL = 110 Ω, RE at 3 V, See Figure 8-8 12
Receiver propagation delay, low-to-high tPLH 47 70 ns VID = -1.5 V to 1.5 V, CL = 15 pF, See Figure 8-10 12
Receiver propagation delay, high-to-low tPHL 49 70 ns VID = -1.5 V to 1.5 V, CL = 15 pF, See Figure 8-10 12
Receiver pulse skew tsk(p) 10 ns /tPHL, tPLH/ 12
Receiver output disable time from high level tPHZ 20 ns DE at 3 V, CL = 15 pF, See Figure 8-11 12
Receiver output enable time to high level tPZH1 20 ns DE at 3 V, CL = 15 pF, See Figure 8-11 12
Receiver standby-to-high-level delay tPZH2 4000 ns DE at 0 V 12
Receiver output disable time from low level tPLZ 20 ns DE at 3 V, CL = 15 pF, See Figure 8-12 12
Receiver output enable time to low level tPZL1 20 ns DE at 3 V, CL = 15 pF, See Figure 8-12 12
Receiver standby-to-low-level delay tPZL2 4000 ns DE at 0 V 12
Receiver output rise time tr 5 ns 12
Receiver output fall time tf 6 ns 12

CAD (KiCad official)

  • Symbol: SN65HVD35DR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn65hvd35dr-etched.step / sn65hvd35dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65hvd35dr.step / sn65hvd35dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (47 pp, sha256 4f90059e9caf3d07, retrieved 2026-10-24, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF