SN65HVD265DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TXD	input	CAN transmit data input (LOW for dominant and HIGH for recessive bus states), pulled up to VCC internally if floating.
2	GND	power_in	Ground connection.
3	VCC	power_in	Transceiver 5V supply voltage, absolute maximum -0.3 V to 6 V.
4	RXD	output	CAN receive data output (LOW for dominant and HIGH for recessive bus states), driven to VCC level on the SN65HVD265.
5	NC	unconnected	SN65HVD265: No Connect.
6	CANL	bidirectional	Low level CAN bus line, bus fault protection -27 V to 40 V.
7	CANH	bidirectional	High level CAN bus line, bus fault protection -27 V to 40 V.
8	S	input	Mode select: silent mode select terminal (active high), pulled down to GND internally so the device defaults to normal mode if floating.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Interface ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	-0.3		6	V		4
CAN bus I/O voltage	VBUS	-27		40	V	CANH, CANL	4
Logic input terminal voltage	V(Logic_Input)	-0.3		6	V	TXD, S	4
Logic output terminal voltage	V(Logic_Output)	-0.3		6	V	RXD, SN65HVD265	4
RXD output current	IO(RXD)			12	mA		4
Operating virtual junction temperature	TJ	-40		150	°C		4
Ambient temperature	TA	-40		125	°C		4
ESD HBM, all pins	V(ESD)	-2500		2500	V	ANSI/ESDA/JEDEC JS-001	4
ESD HBM, CAN bus pins	V(ESD)	-12000		12000	V	CANH, CANL	4
Supply voltage	VCC	4.5		5.5	V		5
CAN bus terminal voltage	VI or VIC	-2		7	V	separately or common mode	5
CAN bus differential voltage	VID	-6		6	V		5
Logic HIGH level input	VIH	2		5.5	V	TXD, S	5
Logic LOW level input	VIL	0		0.8	V	TXD, S	5
CAN bus driver high level output current	IOH(DRVR)	-70			mA		5
CAN bus driver low level output current	IOL(DRVR)			70	mA		5
RXD HIGH level output current	IOH(RXD)	-2			mA		5
RXD LOW level output current	IOL(RXD)			2	mA		5
Operational free-air temperature	TA	-40		125	°C		5
Junction-to-air thermal resistance	RθJA		107.5		°C/W	High-K, D (SOIC) 8 pins	5
Junction-to-board thermal resistance	RθJC(top)		48.9		°C/W	D (SOIC) 8 pins	5
Junction-to-case (top) thermal resistance	RθJB		56.7		°C/W	D (SOIC) 8 pins	5
5-V supply current, normal mode driving dominant	ICC		60	85	mA	TXD = 0 V, RL = 50 Ω, CL = open, RCM = open, S = 0V	5
5-V supply current, dominant bus fault	ICC		130	180	mA	TXD = 0 V, S = 0V, CANH = -12V, RL = open, CL = open, RCM = open	5
5-V supply current, dominant no load	ICC		10	20	mA	TXD = 0 V, RL = open, CL = open, RCM = open, S = 0V	5
5-V supply current, normal mode recessive	ICC		10	20	mA	TXD = VCC, RL = 50 Ω, CL = open, RCM = open, S = 0V	5
5-V supply current, silent mode	ICC		2.5	5	mA	TXD = VCC, RL = 50 Ω, CL = open, RCM = open, S = VCC	5
Undervoltage detection on VCC	UVVCC	3.5		4.45	V	protected mode	5
Hysteresis voltage on UVVCC	VHYS(UVVCC)		200		mV		5
S HIGH-level input voltage	VIH	2			V		6
S LOW-level input voltage	VIL			0.8	V		6
S HIGH-level input leakage current	IIH		7	100	µA	S = VCC = 5.5 V	6
S LOW-level input leakage current	IIL	-1	0	1	µA	S = 0 V, VCC = 5.5 V	6
S unpowered leakage current	Ilkg(OFF)	7	35	100	µA	S = 5.5 V, VCC = 0 V, V(RXD) = 0 V	6
TXD HIGH level input voltage	VIH	2			V		6
TXD LOW level input voltage	VIL			0.8	V		6
TXD HIGH level input leakage current	IIH	-2.5	0	1	µA	TXD = VCC = 5.5 V	6
TXD Low level input leakage current	IIL	-100	-25	-7	µA	TXD = 0 V, VCC = 5.5 V	6
TXD unpowered leakage current	Ilkg(OFF)	-1	0	1	µA	TXD = 5.5 V, VCC = 0 V, V(RXD) = 0 V	6
Input capacitance	CI		3.5		pF		6
RXD LOW level output voltage	VOL			0.4	V	See Figure 5, IO = 2 mA	6
RXD unpowered leakage current	Ilkg(OFF)	-1	0	1	µA	RXD = 5.5 V, VCC = 0 V, V(RXD) = 0 V	6
CANH bus output voltage (dominant)	VO(D)	2.75		4.5	V	TXD = 0 V, S = 0 V, RL = 60 Ω, CL = open, RCM = open	6
CANL bus output voltage (dominant)	VO(D)	0.5		2.25	V	TXD = 0 V, S = 0 V, RL = 60 Ω, CL = open, RCM = open	6
Bus output voltage (recessive)	VO(R)	2		3	V	TXD = VCC, V(RXD) = VCC, S = VCC or 0 V, RL = open (no load), RCM = open	6
Differential output voltage (dominant)	VOD(D)	1.5		3	V	TXD = 0 V, S = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = 330 Ω, -2 V ≤ VCM ≤ 7 V, 4.75 V≤ VCC ≤ 5.25 V	6
Differential output voltage (dominant)	VOD(D)	1.25		3.2	V	TXD = 0 V, S = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = 330 Ω, -2 V ≤ VCM ≤ 7 V, 4.5V ≤ VCC ≤ 5.5 V	6
Differential output voltage (recessive)	VOD(R)	-0.12		0.012	V	TXD = VCC, S = 0 V, RL = 60 Ω, CL = open, RCM = open	6
Differential output voltage (recessive), no load	VOD(R)	-0.1		0.05	V	TXD = VCC, S = 0 V, RL = open (no load), CL = open, RCM = open, -40°C ≤ TA ≤ 85°C	6
Output symmetry (dominant or recessive)	VSYM	-0.4		0.4	V	S at 0 V, RL = 60 Ω, CL = open, RCM = open	6
Short circuit steady-state output current, dominant	IOS(SS_DOM)	-160			mA	VCANH = 0 V, CANL = open, TXD = 0 V	7
Short circuit steady-state output current, dominant	IOS(SS_DOM)			160	mA	VCANL = 32 V, CANH = open, TXD = 0 V	7
Short circuit steady-state output current, recessive	IOS(SS_REC)	-8		8	mA	-20 V ≤ VBUS ≤ 32 V, TXD = VCC, Normal and Silent Modes	7
Positive-going input threshold voltage	VIT+			900	mV	normal mode	7
Negative-going input threshold voltage	VIT-	500			mV	normal mode	7
Hysteresis voltage (VIT+ - VIT-)	VHYS		125		mV		7
Power-off bus input leakage current	Ilkg(IOFF)			5.5	µA	CANH = CANL = 5 V, VCC = 0 V, V(RXD) = 0 V	7
Differential input resistance	RID	30		80	kΩ		7
Input resistance (CANH or CANL)	RIN	15		40	kΩ	TXD = VCC = V(RXD) = 5 V, S = 0 V	7
Input resistance matching	RIN(M)	-3		3	%	V(CANH) = V(CANL), -40°C ≤ TA ≤ 85°C	7
Thermal shutdown temperature			170		°C		7
Total loop delay, recessive to dominant	tPROP(LOOP1)			150	ns	See Figure 7, S = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF	8
Loop delay symmetry for 2Mbps CAN FD	tREC(2Mbps)	400		550	ns	See Figure 8, S = 0 V, RL = 60Ω, CL = 100pF, CL(RXD) = 15pF, tBIT = 500ns	8

CAD (KiCad official)

Symbol: SN65HVD265DR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: sn65hvd265dr-etched.step / sn65hvd265dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65hvd265dr.step / sn65hvd265dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (35 pp, sha256 8efd4739903f27e6, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

SN65HVD265DR

Verified SN65HVD265DR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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