component

SN65HVD232QDR

Public Made by Adom

by adom

Texas Instruments CAN ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icssn65hvd232qdrfactory-2.0.0extractor-text

Verified SN65HVD232QDR

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN65HVD232QDR · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 36-page datasheet
  • ✓distributor: lcsc C177182, digikey 296-52699-2-ND, mouser 595-SN65HVD232QDR
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-31o1qg9e/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.33)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn65hvd232qdr.kicad_sym✓ sn65hvd232qdr.kicad_mod✓ sn65hvd232qdr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10d ago
viewers sn65hvd232qdr: viewers · Ray 10d ago
package.json Publish 0.1.0 · Ray 10d ago
page.json Set visibility: public · Ray 10d ago
README.md Publish 0.1.0 · Ray 10d ago
sn65hvd232qdr-etched.glb Publish 0.1.0 · Ray 10d ago
sn65hvd232qdr-etched.step sn65hvd232qdr: factory component page (tier=mfr) · Ray 10d ago
sn65hvd232qdr-hero.glb sn65hvd232qdr: hero GLB from the etched model (keeps the MPN mark) · Ray 10d ago
sn65hvd232qdr-hero.overlay.json Publish 0.1.0 · Ray 10d ago
sn65hvd232qdr.glb Publish 0.1.0 · Ray 10d ago
sn65hvd232qdr.kicad_mod Publish 0.1.0 · Ray 10d ago
sn65hvd232qdr.kicad_sym Publish 0.1.0 · Ray 10d ago
sn65hvd232qdr.lbr Publish 0.1.0 · Ray 10d ago
sn65hvd232qdr.step Publish 0.1.0 · Ray 10d ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 10d ago

SN65HVD232QDR

Texas Instruments · CAN ICs · SOIC-8

SN65HVD232QDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D input Driver input.
2 GND power_in Ground.
3 VCC power_in Supply voltage (3.3-V operation).
4 R output Receiver output.
5 NC unconnected No internal connection.
6 CANL bidirectional Low bus output (CAN low-level bus line).
7 CANH bidirectional High bus output (CAN high-level bus line).
8 NC unconnected No internal connection.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.3 6 V 6
Voltage range at any bus terminal -7 16 V CANH or CANL 6
Transient pulse voltage CANH/CANL -25 25 V through 100 Ω, Figure 7 6
ESD HBM CANH, CANL and GND 15 kV Human body model 6
ESD HBM all pins 2.5 kV Human body model 6
ESD CDM all pins 4 kV Charged-device model 6
Storage temperature range Tstg -65 150 °C 6
Lead temperature 260 °C 1,6 mm from case for 10 seconds 6
Power rating D package 725 mW TA ≤ 25°C 6
Derating factor D package 5.8 mW/°C above TA = 25°C 6
Power rating D package 464 mW TA = 70°C 6
Power rating D package 377 mW TA = 85°C 6
Power rating D package 145 mW TA = 125°C 6
Supply voltage VCC 3 3.6 V 6
Voltage at any bus terminal (common mode) VIC -2 7 V 6
Voltage at any bus terminal (separately) VI -2.5 7.5 V 6
High-level input voltage VIH 2 V D, R 6
Low-level input voltage VIL 0.8 V D, R 6
Differential input voltage VID -6 6 V see Figure 5 6
High-level output current, driver IOH -40 mA Driver 6
High-level output current, receiver IOH -8 mA Receiver 6
Low-level output current, driver IOL 48 mA Driver 6
Low-level output current, receiver IOL 8 mA Receiver 6
Operating free-air temperature TA -40 125 °C 6
Bus output voltage dominant CANH VO(CANH) 2.45 V VI = 0 V, See Figure 1 and Figure 3 7
Bus output voltage dominant CANL VO(CANL) 1.25 V VI = 0 V, See Figure 1 and Figure 3 7
Differential output voltage dominant VOD(D) 1.5 2 3 V VI = 0 V, See Figure 1 7
Differential output voltage dominant VOD(D) 1.2 2 3 V VI = 0 V, See Figure 2 7
Differential output voltage recessive VOD(R) -120 0 12 mV VI = 3 V, See Figure 1 7
Differential output voltage recessive VOD(R) -0.5 -0.2 0.05 V VI = 3 V, No load 7
High-level input current IIH -30 µA VI = 2 V 7
Low-level input current IIL -30 µA VI = 0.8 V 7
Short-circuit output current IOS -250 250 mA VCANH = -2 V 7
Supply current dominant ICC 10 17 mA VI = 0 V, No load 7
Supply current recessive ICC 10 17 mA VI = VCC, No load 7
Driver propagation delay low-to-high tPLH 35 85 ns CL = 50 pF, See Figure 4, TA = 25°C 8
Driver propagation delay high-to-low tPHL 70 120 ns CL = 50 pF, See Figure 4, TA = 25°C 8
Driver pulse skew tsk(p) 35 ns CL = 50 pF, See Figure 4 8
Driver differential output rise time tr 25 50 100 ns CL = 50 pF, See Figure 4 8
Driver differential output fall time tf 40 55 80 ns CL = 50 pF, See Figure 4 8
Positive-going input threshold voltage VIT+ 900 mV See Table 1 8
Negative-going input threshold voltage VIT− 500 mV See Table 1 8
Hysteresis voltage Vhys 100 mV 8
High-level output voltage VOH 2.4 V -6 V ≤ VID ≤ 500 mV, IO = -8 mA, See Figure 5 8
Low-level output voltage VOL 0.4 V 900 mV ≤ VID ≤ 6 V, IO = 8 mA, See Figure 5 8
Differential input resistance Rdiff 40 70 100 kΩ Pin-to-pin, V(D) = 3 V 8
CANH, CANL input resistance RT 20 35 50 kΩ 8
CANH, CANL input capacitance Ci 32 pF Pin-to-ground, VI = 0.4 sin(4E6πt) + 0.5 V, V(D) = 3 V 8
Differential input capacitance Cdiff 16 pF Pin-to-pin, VI = 0.4 sin(4E6πt) + 0.5 V, V(D) = 3 V 8
Receiver propagation delay low-to-high tPLH 35 50 ns See Figure 6, TA = 25°C 8
Receiver propagation delay high-to-low tPHL 35 50 ns See Figure 6, TA = 25°C 8
Receiver pulse skew tsk(p) 10 ns See Figure 6 8
Receiver output rise time tr 1.5 ns See Figure 6 8
Receiver output fall time tf 1.5 ns See Figure 6 8

CAD (KiCad official)

  • Symbol: SN65HVD232QDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: sn65hvd232qdr-etched.step / sn65hvd232qdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65hvd232qdr.step / sn65hvd232qdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 275feb27291ab482, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF