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SN65HVD230QDG4Q1

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Texas Instruments CAN Transceivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Verified SN65HVD230QDG4Q1

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN65HVD230QDG4Q1 · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 36-page datasheet
  • ✓distributor: lcsc C1543960, digikey 296-23353-5-ND, mouser 595-SN65HVD230QDG4Q1
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-a75lc4he/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn65hvd230qdg4q1.kicad_sym✓ sn65hvd230qdg4q1.kicad_mod✓ sn65hvd230qdg4q1.step
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Ray Publish 0.1.0 3f87a49 4h ago

SN65HVD230QDG4Q1

Texas Instruments · CAN Transceivers · SOIC-8

SN65HVD230QDG4Q1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D input Driver input; a low level on D drives the bus dominant (CANH high, CANL low).
2 GND power_in Ground reference for the transceiver.
3 VCC power_in Supply voltage input for the 3.3-V CAN transceiver.
4 R output Receiver output; high when VID ≤ 0.5 V and low when VID ≥ 0.9 V.
5 Vref power_in Reference output available as a VCC/2 voltage reference.
6 CANL bidirectional Low CAN bus output (differential bus line), operating over the -2 V to 7 V common-mode range.
7 CANH bidirectional High CAN bus output (differential bus line), operating over the -2 V to 7 V common-mode range.
8 RS input Standby/slope control: above 0.75 VCC selects standby, a 10 kΩ to 100 kΩ resistor to ground sets slope control, and below 1 V selects high-speed mode.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 3 3.6 V 6
Voltage at any bus terminal (common mode) VIC -2 7 V 6
Voltage at any bus terminal (separately) VI -2.5 7.5 V 6
High-level input voltage VIH 2 V D, R 6
Low-level input voltage VIL 0.8 V D, R 6
Differential input voltage VID -6 6 V see Figure 5 6
Rs wave-shaping resistance Rs 0 100 kΩ 6
High-level output current, driver IOH -40 mA Driver 6
High-level output current, receiver IOH -8 mA Receiver 6
Low-level output current, driver IOL 48 mA Driver 6
Low-level output current, receiver IOL 8 mA Receiver 6
Operating free-air temperature TA -40 125 °C 6
Supply voltage range VCC -0.3 6 V 6
Voltage range at any bus terminal (CANH or CANL) -7 16 V 6
Voltage input range, transient pulse, CANH and CANL -25 25 V through 100 Ω, see Figure 7 6
Storage temperature range Tstg -65 150 °C 6
Lead temperature 260 °C 1,6 mm from case for 10 seconds 6
Continuous total power dissipation, D package 725 mW TA ≤ 25°C 6
Driver dominant bus output voltage CANH VOH 2.45 V Dominant, VI = 0 V 7
Driver dominant bus output voltage CANL VOL 0.5 1.25 V Dominant, VI = 0 V, See Figure 1 and Figure 3 7
Differential output voltage dominant VOD(D) 1.5 2 3 V Dominant, VI = 0 V, See Figure 1 7
Differential output voltage dominant VOD(D) 1.2 2 3 V Dominant, VI = 0 V, See Figure 2 7
Differential output voltage recessive VOD(R) -120 0 12 mV Recessive, VI = 3 V, See Figure 1 7
Differential output voltage recessive VOD(R) -0.5 -0.2 0.05 V Recessive, VI = 3 V, No load 7
Short circuit output current IOS -250 250 mA VCANH = -2 V 7
Supply current standby (SN65HVD230Q) ICC 370 600 µA Standby, SN65HVD230Q 7
Supply current dominant ICC 10 17 mA All devices, Dominant, VI = 0 V, No load 7
Supply current recessive ICC 10 17 mA All devices, Recessive, VI = VCC, No load 7
Driver propagation delay time, low-to-high tPLH 35 85 ns V(RS) = 0 V 7
Driver propagation delay time, low-to-high tPLH 70 125 ns RS with 10 kΩ to ground 7
Driver propagation delay time, low-to-high tPLH 500 870 ns RS with 100 kΩ to ground 7
Driver propagation delay time, high-to-low tPHL 70 120 ns V(RS) = 0 V 7
Driver propagation delay time, high-to-low tPHL 130 180 ns RS with 10 kΩ to ground 7
Driver propagation delay time, high-to-low tPHL 870 1200 ns RS with 100 kΩ to ground 7
Driver pulse skew tsk(p) 35 ns V(RS) = 0 V 7
Driver pulse skew tsk(p) 60 ns RS with 10 kΩ to ground, CL = 50 pF, See Figure 4 7
Driver pulse skew tsk(p) 370 ns RS with 100 kΩ to ground, See Figure 4 7
Differential output signal rise time tr 25 50 100 ns V(RS) = 0 V 7
Differential output signal fall time tf 40 55 80 ns V(RS) = 0 V 7
Differential output signal rise time tr 80 120 160 ns RS with 10 kΩ to ground 7
Differential output signal fall time tf 80 125 150 ns RS with 10 kΩ to ground 7
Differential output signal rise time tr 600 800 1200 ns RS with 100 kΩ to ground 7
Differential output signal fall time tf 600 825 1000 ns RS with 100 kΩ to ground 7
Positive-going input threshold voltage VIT+ 750 900 mV See Table 1 8
Negative-going input threshold voltage VIT− 500 650 mV See Table 1 8
Hysteresis voltage Vhys 100 mV VIT+ − VIT− 8
High-level output voltage VOH 2.4 V −6 V ≤ VID ≤ 500 mV, IO = −8 mA, See Figure 5 8
Low-level output voltage VOL 0.4 V 900 mV ≤ VID ≤ 6 V, IO = 8 mA, See Figure 5 8
Bus input current II 100 250 µA VIH = 7 V 8
Bus input current II -200 -30 µA VIH = −2 V, Other input at 0 V, D = 3 V 8
Differential input resistance Rdiff 40 70 100 kΩ Pin-to-pin, V(D) = 3 V 8
CANH, CANL input resistance RT 20 35 50 kΩ 8
Receiver propagation delay time, low-to-high tPLH 35 50 ns See Figure 6 8
Receiver propagation delay time, high-to-low tPHL 35 50 ns See Figure 6 8
Total loop delay, driver input to receiver output t(loop) 70 135 ns V(RS) = 0 V 8
Total loop delay, driver input to receiver output t(loop) 105 175 ns RS with 10 kΩ to ground 8
Total loop delay, driver input to receiver output t(loop) 535 920 ns RS with 100 kΩ to ground 8
SN65HVD230Q wake-up time from standby mode t(WAKE) 0.55 1.5 µS with RS, See Figure 8 9
Input current for high-speed mode I(RS) -450 0 µA V(RS) < 1 V 9

CAD (KiCad official)

  • Symbol: SN65HVD230QDG4Q1
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: sn65hvd230qdg4q1-etched.step / sn65hvd230qdg4q1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65hvd230qdg4q1.step / sn65hvd230qdg4q1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 275feb27291ab482, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF