component

SN65HVD1781DR

Public Made by Adom

by adom

Texas Instruments RS-485 / RS-422 ICs, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs sn65hvd1781dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json sn65hvd1781dr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1d ago
README.md sn65hvd1781dr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
sn65hvd1781dr-etched.fit.json sn65hvd1781dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
sn65hvd1781dr-etched.glb sn65hvd1781dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
sn65hvd1781dr-etched.step sn65hvd1781dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
sn65hvd1781dr.glb Publish 0.1.0 · Ray 1mo ago
sn65hvd1781dr.kicad_mod Publish 0.1.0 · Ray 1mo ago
sn65hvd1781dr.kicad_sym Publish 0.1.0 · Ray 1mo ago
sn65hvd1781dr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 8 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
sn65hvd1781dr.step Publish 0.1.0 · Ray 1mo ago

SN65HVD1781DR

Texas Instruments · RS-485 / RS-422 ICs · SOIC-8

SN65HVD1781DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 R output Receiver data output. CMOS-level output presenting the demodulated state of the differential bus (A vs B). Drives up to ±8 mA (VOH ≥ 2.4 V, VOL ≤ 0.4 V).
2 RE input Receiver enable, active low. Drive low (or tie to GND) to enable the receiver output R; drive high (or tie to VCC) to place R in high-impedance. Combine with DE=low for standby/low-power mode.
3 DE input Driver enable, active high. Drive high to enable the differential driver (A/B); drive low to place the driver outputs in high-impedance. Combine with RE=high for standby/low-power mode (ICC ≤ 1 µA).
4 D input Driver data input. CMOS logic input whose state (with DE=high) sets the differential polarity between bus pins A and B. VIH ≥ 2 V, VIL ≤ 0.8 V.
5 GND power_in Ground reference for the device. Connect to the system ground plane.
6 A bidirectional Non-inverting RS-485 bus I/O. Driver output or receiver input, complementary to B. Fault-protected to ±70 V and ±16 kV HBM ESD; withstands -7 V to +12 V common-mode in normal operation.
7 B bidirectional Inverting RS-485 bus I/O. Driver output or receiver input, complementary to A. Fault-protected to ±70 V and ±16 kV HBM ESD; withstands -7 V to +12 V common-mode in normal operation.
8 VCC power_in Positive supply. 3.15 V to 5.5 V recommended operating range (4.5 V to 5.5 V per Pin Functions table for full RS-485 compliance). Bypass locally with a 0.1 µF ceramic capacitor to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Interface
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • SN65HVD1781DR
  • SN65HVD1781DRD
  • SN65HVD1781DRP

CAD (KiCad official)

  • Symbol: SN65HVD1781DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: sn65hvd1781dr-etched.step / sn65hvd1781dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65hvd1781dr.step / sn65hvd1781dr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sn65hvd1781dr.step 122 KB You want the bare part, or you mark your own boards.
sn65hvd1781dr-etched.step 2.4 MB You want the part with SN65HVD1781DR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 608 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 f8736dab94b48730, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF