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SN65HVD12EIM

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HGSEMI Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN65HVD12EIM

HGSEMI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOP-8

SN65HVD12EIM from HGSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 R output Receiver output, high-impedance when RE is high; drives high for VID ≥ -0.01 V and low for VID ≤ -0.2 V, rated for 8 mA output current.
2 RE input Active-low receiver enable input; logic levels VIL 0 to 0.8 V and VIH 2 V to VCC, with RE high and DE low placing the device in standby.
3 DE input Active-high driver enable input; logic levels VIL 0 to 0.8 V and VIH 2 V to VCC, with DE low giving high-impedance driver outputs.
4 D input Driver data input; logic levels VIL 0 to 0.8 V and VIH 2 V to VCC, with D high giving A high and B low when DE is high.
5 GND power_in Ground (network ground reference) with ±16 kV HBM ESD protection.
6 A bidirectional Non-inverting bus I/O (driver output and receiver input) with ±16 kV HBM ESD, short-circuit protected from -7 V to 12 V.
7 B bidirectional Inverting bus I/O (driver output and receiver input) with ±16 kV HBM ESD, short-circuit protected from -7 V to 12 V.
8 VCC power_in Supply voltage input, recommended 3 V to 3.6 V, absolute maximum -0.3 V to 6 V.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package SOP-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC VCC -0.3 6 V 2
Voltage range at A or B -9 14 V 2
Input voltage range at D, DE, R or RE -0.5 V 2
Voltage input range, transient pulse, A and B -50 50 V through 100 Ω, see Figure 11 2
Receiver output current IO -11 11 mA 2
ESD human body model, A, B, and GND -16 16 kV Human body model 2
ESD human body model, all pins -4 4 kV Human body model 2
ESD charged-device model, all pins -1 1 kV Charged-device model 2
Electrical fast transient/burst, A, B, and GND -4 4 kV IEC 61000-4-4 2
Junction temperature TJ 170 °C 2
Lead temperature (soldering) 260 °C 10 seconds 2
Supply voltage VCC 3 3.6 V 3
Voltage at any bus terminal (separately or common mode) VI or VIC -7 12 V 3
High-level input voltage D, DE, RE VIH 2 V 3
Low-level input voltage D, DE, RE VIL 0 0.8 V 3
Differential input voltage VID -12 12 V Figure 7 3
High-level output current, driver IOH -60 mA Driver 3
High-level output current, receiver IOH -8 mA Receiver 3
Low-level output current, driver IOL 60 mA Driver 3
Low-level output current, receiver IOL 8 mA Receiver 3
Differential load resistance RL 54 60 Ω 3
Differential load capacitance CL 50 pF 3
Signaling rate, HVD12 1 Mbps 3
Junction temperature (recommended) TJ 145 °C 3
Input clamp voltage VIK -1.5 V II = -18 mA 3
Differential output voltage /VOD/ 2 V IO = 0 3
Differential output voltage, RL = 54 Ω /VOD/ 1.5 V RL = 54 Ω, See Figure 1 3
Differential output voltage with common-mode loading /VOD/ 1.5 V Vtest = -7 V to 12 V, See Figure 2 3
Change in magnitude of differential output voltage Δ/VOD/ -0.2 0.2 V See Figure 1 and Figure 2 3
Peak-to-peak common-mode output voltage VOC(PP) 400 mV See Figure 3 3
Steady-state common-mode output voltage VOC(SS) 1.4 2.5 V 3
Change in steady-state common-mode output voltage ΔVOC(SS) -0.05 0.05 V 3
Input current, D II -100 0 μA 3
Input current, DE II 0 100 μA 3
Short-circuit output current IOS -250 250 mA -7 V ≤ VO ≤ 12 V 3
Supply current, receiver disabled and driver enabled ICC 9 15.5 mA RE at VCC, D & DE at VCC, No load 3
Supply current, standby (receiver and driver disabled) ICC 1 5 μA RE at VCC, D at VCC, DE at 0 V, No load 3
Supply current, receiver enabled and driver enabled (driver table) ICC 9 15.5 mA RE at 0 V, D & DE at VCC, No load 3
Propagation delay time, low-to-high-level output, HVD12 tPLH 135 200 300 ns RL = 54 Ω, CL = 50 pF, See Figure 4 4
Propagation delay time, high-to-low-level output, HVD12 tPHL 135 200 300 ns RL = 54 Ω, CL = 50 pF, See Figure 4 4
Differential output signal rise time, HVD12 tr 100 170 300 ns RL = 54 Ω, CL = 50 pF, See Figure 4 4
Differential output signal fall time, HVD12 tf 100 170 300 ns RL = 54 Ω, CL = 50 pF, See Figure 4 4
Positive-going input threshold voltage VIT+ -0.065 -0.01 V IO = -8 mA 5
Negative-going input threshold voltage VIT- -0.2 -0.1 V IO = 8 mA 5
Enable-input clamp voltage VIK -1.5 V II = -18 mA 5
High-level output voltage VOH 2.4 V VID = 200 mV, IOH = -8 mA, See Figure 7 5
Low-level output voltage VOL 0.4 V VID = -200 mV, IOL = 8 mA, See Figure 7 5
High-impedance-state output current IOZ -1 1 μA VO = 0 or VCC, RE at VCC 5
Bus input current, VA or VB = 12 V (HVD12) II 0.05 0.11 mA VA or VB = 12 V, HVD11, HVD12, other input at 0 V 5
Bus input current, VA or VB = 12 V, VCC = 0 V (HVD12) II 0.06 0.13 mA VA or VB = 12 V, VCC = 0 V, HVD11, HVD12, other input at 0 V 5
Bus input current, VA or VB = -7 V (HVD12) II -0.1 -0.05 mA VA or VB = -7 V, HVD11, HVD12, other input at 0 V 5
Bus input current, VA or VB = -7 V, VCC = 0 V (HVD12) II -0.05 -0.04 mA VA or VB = -7 V, VCC = 0 V, HVD11, HVD12, other input at 0 V 5
High-level input current, RE IIH -30 0 μA VIH = 2 V 5
Low-level input current, RE IIL -30 0 μA VIL = 0.8 V 5
Supply current, receiver enabled and driver disabled ICC 4 8 mA RE at 0 V, D & DE at 0 V, No load 5
Supply current, standby (receiver and driver disabled) ICC 1 5 μA RE at VCC, D at VCC, DE at 0 V, No load 5
Supply current, receiver enabled and driver enabled (receiver table) ICC 9 15.5 mA RE at 0 V, D & DE at VCC, No load 5
Propagation delay time, low-to-high-level output, HVD12 tPLH 30 55 70 ns VID = -1.5 V to 1.5 V, CL = 15 pF, See Figure 8 6
Propagation delay time, high-to-low-level output, HVD12 tPHL 30 55 70 ns VID = -1.5 V to 1.5 V, CL = 15 pF, See Figure 8 6
Output signal rise time tr 1 2 5 ns CL = 15 pF, See Figure 8 6

CAD (KiCad official)

  • Symbol: SN65HVD12EIM
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: sn65hvd12eim-etched.step / sn65hvd12eim-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65hvd12eim.step / sn65hvd12eim.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (18 pp, sha256 d558e909f9bfc353, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF