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Contents

README

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SN65DP159RGZR

Texas Instruments · Telecom Interface ICs · VQFN-48-EP(7x7)

SN65DP159RGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SWAP/POL input Three-level input lane SWAP and polarity control pin when I2C_EN/PIN = Low. H: receive polarity swap (retimer mode only); L: receive lanes swap (retimer and redriver mode); NC: normal working. RGZ package only.
2 IN_D2p input Main link channel 2 differential input (positive). AC-coupled TMDS/DP dual-mode input, fail-safe.
3 IN_D2n input Main link channel 2 differential input (negative). AC-coupled TMDS/DP dual-mode input, fail-safe.
4 HPD_SRC output Hot Plug Detect output, source side (toward GPU/upstream).
5 IN_D1p input Main link channel 1 differential input (positive). AC-coupled TMDS/DP dual-mode input, fail-safe.
6 IN_D1n input Main link channel 1 differential input (negative). AC-coupled TMDS/DP dual-mode input, fail-safe.
7 GND power_in Ground reference.
8 IN_D0p input Main link channel 0 differential input (positive). AC-coupled TMDS/DP dual-mode input, fail-safe.
9 IN_D0n input Main link channel 0 differential input (negative). AC-coupled TMDS/DP dual-mode input, fail-safe.
10 I2C_EN/PIN input Mode select: High puts device into I2C control mode; Low puts device into pin-strap mode.
11 IN_CLKp input Main link clock differential input (positive). AC-coupled TMDS/DP dual-mode input.
12 IN_CLKn input Main link clock differential input (negative). AC-coupled TMDS/DP dual-mode input.
13 VCC power_in 3.3-V power supply.
14 VDD power_in 1.1-V core power supply.
15 SCL_CTL input I2C clock signal input. When I2C_EN/PIN = Low, pin-strap configuration takes priority and I2C cannot override those functions.
16 SDA_CTL bidirectional I2C data signal. When I2C_EN/PIN = Low, pin-strap configuration takes priority and I2C cannot override those functions.
17 NC unconnected No connect. (RGZ package only; leave unconnected.)
18 CEC_EN output CEC control pin for HDMI dongle applications. RGZ package only.
19 GND power_in Ground reference.
20 PRE_SEL input De-emphasis pin-strap when I2C_EN/PIN = Low. Three-level: L = -2 dB de-emphasis, NC = 0 dB, H = Reserved.
21 EQ_SEL/A0 input Input receive equalization pin-strap when I2C_EN/PIN = Low (three-level: L = 7.5 dB fixed, NC = adaptive, H = 14 dB fixed). When I2C_EN/PIN = High, this pin selects I2C address bit 1 (2-level).
22 VSADJ passive TMDS-compliant transmit voltage swing control. Connect a nominal resistor to GND to set output swing amplitude.
23 VDD power_in 1.1-V core power supply.
24 VDD power_in 1.1-V core power supply.
25 OUT_CLKn output TMDS data clock differential output (negative). Fail-safe.
26 OUT_CLKp output TMDS data clock differential output (positive). Fail-safe.
27 HDMI_SEL/A1 input When I2C_EN/PIN = Low: HDMI_SEL H = DVI, L = HDMI (Adapter ID readable through I2C or I2C-over-AUX). When I2C_EN/PIN = High: acts as I2C address bit 2. Weak internal pull-down.
28 OUT_D0n output TMDS data 0 differential output (negative). Fail-safe.
29 OUT_D0p output TMDS data 0 differential output (positive). Fail-safe.
30 GND power_in Ground reference.
31 OUT_D1n output TMDS data 1 differential output (negative). Fail-safe.
32 OUT_D1p output TMDS data 1 differential output (positive). Fail-safe.
33 HPD_SNK input Hot Plug Detect input, sink side (from monitor/downstream). Fail-safe.
34 OUT_D2n output TMDS data 2 differential output (negative). Fail-safe.
35 OUT_D2p output TMDS data 2 differential output (positive). Fail-safe.
36 TX_TERM_CTL input Transmit termination control when I2C_EN/PIN = Low. Three-level: H = no termination; L = 75-150 Ω termination; NC = automatic selection based on data rate. RGZ package only.
37 VDD power_in 1.1-V core power supply.
38 SCL_SNK bidirectional Sink-side TMDS/DDC bidirectional clock line (toward monitor). Fail-safe.
39 SDA_SNK bidirectional Sink-side TMDS/DDC bidirectional data line (toward monitor). Fail-safe.
40 SLEW_CTL input Slew rate control when I2C_EN/PIN = Low. Three-level: H = fastest data rate; L = 5 ps slow; NC = 10 ps slow. When I2C_EN/PIN = High, slew is controlled via I2C.
41 GND power_in Ground reference.
42 OE input Operation enable / reset. OE = L: power-down mode; OE = H: normal operation. Internal weak pull-up; resets device on H-to-L transition.
43 VCC power_in 3.3-V power supply.
44 AUX_SRCn bidirectional Source-side bidirectional DisplayPort AUX / I2C-over-AUX, negative. DP159 RGZ package only.
45 AUX_SRCp bidirectional Source-side bidirectional DisplayPort AUX / I2C-over-AUX, positive. DP159 RGZ package only.
46 SCL_SRC bidirectional Source-side TMDS/DDC bidirectional clock line (toward GPU).
47 SDA_SRC bidirectional Source-side TMDS/DDC bidirectional data line (toward GPU).
48 VDD power_in 1.1-V core power supply.
PAD GND power_in Exposed thermal pad. Connect to ground plane for electrical ground return and heat sinking.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Interface
Pins 49

Ordering variants

Same part, different packaging or reel option.

  • SN65DP159RGZR
  • SN65DP159RGZRRGZT
  • SN65DP159RGZRRSBR
  • SN65DP159RGZRRSBT

CAD (KiCad official)

  • Symbol: SN65DP159RGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: sn65dp159rgzr-etched.step / sn65dp159rgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65dp159rgzr.step / sn65dp159rgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (64 pp, sha256 9899cd2a6d5fe32e, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF