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SN65CML100DR
Public Made by Adomby adom
Texas Instruments Translators, Level Shifters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN65CML100DR
Texas Instruments · Translators, Level Shifters · SOIC-8
SN65CML100DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No-connect pin with no internal connection; the datasheet lists it only as NC in the pin assignments and pin descriptions. |
| 2 | A | input | Non-inverting differential receiver input, compatible with LVDS, LVPECL and CML levels, with a 0 V to 4 V input voltage range and a differential input magnitude |
| 3 | B | input | Inverting differential receiver input, compatible with LVDS, LVPECL and CML levels, with a 0 V to 4 V input voltage range and a differential input magnitude |
| 4 | VBB | power_out | Internally generated reference voltage output for single-ended LVPECL input; when used it must be decoupled with a 0.01-µF capacitor, sourcing or sinking must be limited to 400 µA, and it should be left open when not used. |
| 5 | GND | power_in | Ground reference for the device, to which all voltages are referenced (network ground). |
| 6 | Z | output | Differential CML driver output (inverted polarity with respect to Y), intended to drive 50-Ω or 25-Ω loads terminated to VTT. |
| 7 | Y | output | Differential CML driver output, intended to drive 50-Ω or 25-Ω loads terminated to VTT. |
| 8 | VCC | power_in | Positive supply, rated 3 V to 3.6 V (3.3 V nominal) with an absolute maximum of 4 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Logic |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
SN65CML100DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
sn65cml100dr-etched.step/sn65cml100dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn65cml100dr.step/sn65cml100dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
21ca23b126bf8e2e, retrieved 2026-10-10, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN65CML100DR
**Texas Instruments** · Translators, Level Shifters · SOIC-8
SN65CML100DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No-connect pin with no internal connection; the datasheet lists it only as NC in the pin assignments and pin descriptions. |
| 2 | A | input | Non-inverting differential receiver input, compatible with LVDS, LVPECL and CML levels, with a 0 V to 4 V input voltage range and a differential input magnitude |VID| of 0.1 V to 1 V. |
| 3 | B | input | Inverting differential receiver input, compatible with LVDS, LVPECL and CML levels, with a 0 V to 4 V input voltage range and a differential input magnitude |VID| of 0.1 V to 1 V. |
| 4 | VBB | power_out | Internally generated reference voltage output for single-ended LVPECL input; when used it must be decoupled with a 0.01-µF capacitor, sourcing or sinking must be limited to 400 µA, and it should be left open when not used. |
| 5 | GND | power_in | Ground reference for the device, to which all voltages are referenced (network ground). |
| 6 | Z | output | Differential CML driver output (inverted polarity with respect to Y), intended to drive 50-Ω or 25-Ω loads terminated to VTT. |
| 7 | Y | output | Differential CML driver output, intended to drive 50-Ω or 25-Ω loads terminated to VTT. |
| 8 | VCC | power_in | Positive supply, rated 3 V to 3.6 V (3.3 V nominal) with an absolute maximum of 4 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Logic |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `SN65CML100DR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `sn65cml100dr-etched.step` / `sn65cml100dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn65cml100dr.step` / `sn65cml100dr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn65cml100.pdf) (23 pp, sha256 `21ca23b126bf8e2e`, retrieved 2026-10-10, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn65cml100dr-datasheet.pdf)