SN6505AQDBVTQ1 from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	D1	output	Open drain output of the first power MOSFETs, typically connected to the outer terminals of the center tap transformer, with external traces kept short because of large currents.
2	VCC	power_in	Device supply pin that should be bypassed with a 4.7 μF or greater low ESR capacitor, and an internal undervoltage lockout turns both outputs off when VCC ≤ 2.25 V.
3	D2	output	Open drain output of the second power MOSFETs, typically connected to the outer terminals of the center tap transformer, with external traces kept short because of large currents.
4	GND	power_in	Ground connected to the power MOSFET sources via an internal sense circuit, which must be tied to a low-inductance quality ground plane because of large currents.
5	EN	input	Enable pin that turns the device on or off, where grounding or leaving it floating disables all internal circuitry and it should be tied directly to VCC if unused.
6	CLK	input	External clock input that is internally pulled down to GND, and the device automatically switches to the internal clock if no valid clock is detected.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOT-23-6
Category	Power Management (PMIC)
Pins	6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	2.25		5.5	V		4
Output switch current - primary side	ID1, ID2			0.75	A	2.25 V ≤ VCC ≤ 2.8 V	4
Output switch current - primary side	ID1, ID2			1	A	2.8 V < VCC ≤ 5.5 V	4
Ambient temperature	TA	-40		125	°C		4
Supply voltage	VCC	-0.5		6	V		4
Voltage on EN, CLK		-0.5			V	max VCC + 0.5 V; must not exceed 6 V	4
Output switch voltage	D1, D2			16	V		4
Peak output switch current	I(D1)Pk, I(D2)Pk			2.4	A		4
Junction temperature	TJ	-40		150	°C		4
Storage temperature range	Tstg	-65		150	°C		4
Junction-to-ambient thermal resistance	RθJA		137.7		°C/W	DBV (SOT-23) 6 pins	4
Junction-to-case (top) thermal resistance	RθJC(top)		57.7		°C/W	DBV (SOT-23) 6 pins	4
Junction-to-board thermal resistance	RθJB		46		°C/W	DBV (SOT-23) 6 pins	4
Junction-to-top characterization parameter	ψJT		13.4		°C/W	DBV (SOT-23) 6 pins	4
Junction-to-board characterization parameter	ψJB		44.9		°C/W	DBV (SOT-23) 6 pins	4
Supply current (SN6505A-Q1)	I(Vcc)		1	1.4	mA	2.8 V ≤ VCC ≤ 5.5 V; RL = 50 Ω	5
Leakage current on EN and CLK pin	IIH		10	20	µA	EN / CLK = VCC	5
VCC current for EN = 0	IDIS		0.1		µA	EN = 0	5
Leakage current on D1	ILKG(D1)		0.1		µA	EN=0; Voltage of D1, D2 = VCC	5
Leakage current on D2	ILKG(D2)		0.1		µA	EN=0; Voltage of D1, D2 = VCC	5
Positive-going UVLO threshold	VCC+ (UVLO)		2.25		V		5
Negative-going UVLO threshold	VCC- (UVLO)		1.7		V		5
UVLO threshold hysteresis	VHYS (UVLO1)		0.3		V		5
D1, D2 average switching frequency (SN6505A-Q1)	FSW	138	160	203	kHz	RL = 50 Ω to VCC; Refer to Figure 7-3	5
External clock frequency on CLK pin (SN6505A-Q1)	F(EXT)	100		600	kHz		5
Average ON time mismatch between D1 and D2	DMM		0		%	RL = 50 Ω	5
Output switch on resistance	R(ON)		0.16	0.25	Ω	VCC = 4.5 V, ID1, ID2 = 1 A	5
Output switch on resistance	R(ON)		0.19	0.31	Ω	VCC = 2.8 V, ID1, ID2 = 1 A	5
Output switch on resistance	R(ON)		0.21	0.45	Ω	VCC = 2.25 V, ID1, ID2 = 0.5 A	5
Voltage slew rate on D1 and D2 (SN6505A-Q1)	V(SLEW)		48		V/µs	RL = 50 Ω to VCC; Refer to Figure 7-3	5
Current slew rate at D1 and D2 (SN6505A-Q1)	I(SLEW)		11		A/µs	RL = 5 Ω through transformer; Refer to Figure 7-4	5
Current clamp limit	ILIM	1.42	1.75	2.15	A	2.8 V < VCC ≤ 5.5 V	5
Current clamp limit	ILIM	0.65		1.85	A	2.25 V ≤ VCC ≤ 2.8 V	5
TSD turn on temperature	TSD+	154	168	181	°C		5
TSD turn off temperature	TSD-	135	150	166	°C		5
TSD hysteresis	TSD-	13		17	°C		5
Duration after which device switches to internal clock on invalid external clock	tCLKTIMER	10		25	µs		6
Break-before-make time (SN6505A-Q1)	tBBM		115		ns	Measured as voltage with RL = 50 Ω to VCC; Refer to Figure 7-3	6
Soft-start time (SN6505A-Q1)	tSS	1	2.2	8	ms	10% to 90% transition time on VOUT; transformer CLOAD = 40 µF; RL = 5 Ω	6
Soft-start time delay	tSSdelay	3.5	8.5	18	ms	From power up to 90% transition time on VOUT; transformer CLOAD = 40 µF; RL = 5 Ω	6
Power down time	tPWRDN	1		5	µs	From EN=0 to output MOSFETs off (no current on D1 and D2)	6

CAD (KiCad official)

Symbol: SN6505AQDBVTQ1
Footprint: Package_TO_SOT_SMD:SOT-23-6
3D model: SOT-23-6 (KiCad packages3D, STEP)
3D model files: sn6505aqdbvtq1-etched.step / sn6505aqdbvtq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn6505aqdbvtq1.step / sn6505aqdbvtq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (40 pp, sha256 3c8af11607815139, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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SN6505AQDBVTQ1

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