# SN3948

**ISSI Integrated Silicon Solution** · DC-DC Converters · SOP-8

SN3948 from ISSI Integrated Silicon Solution, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Chip supply pin, internally regulated to 5 V typical (clamp 4.4 V to 5.6 V at Rin = 10 kΩ), with a maximum VCC input current of 10 mA before the clamp may fail. |
| 2 | TOFF | input | Resistor to GND sets the minimum constant off-time of the NMOS; the datasheet gives 10 µs at Rext = 250 kΩ and recommends about 1 µs typical. |
| 3 | ADJ | input | Chip enable and input peak-current threshold control: below 0.5 V the NMOS is held off, 0.5 V to 2.4 V sets VCSTH = VADJ/10, above 2.4 V VCSTH is fixed at 0.24 V, and when floating it is pulled up internally to 4.5 V (VCSTH = 0.24 V). |
| 4 | GND | power_in | Ground pin for the controller; the Rfb ground return should run short and wide to this pin for output-current accuracy. |
| 5 | GATE | output | Gate drive output for the external NMOS switch, with gate drive current set by switching frequency and the NMOS gate charge. |
| 6 | CS | input | Input peak-current sense pin fed from the resistor Rcs between the NMOS source and GND; the sense threshold VCSTH is 215 mV to 265 mV (240 mV typical) at ADJ = 5 V. |
| 7 | FB | input | Output-current sense pin fed from the external sense resistor Rfb in series with the LED string; the feedback threshold is 0.29 V to 0.31 V (0.3 V typical), so Iout = 0.3 V / Rfb. |
| 8 | OVP | input | Overvoltage-protection sense pin: when the voltage on this pin exceeds 1 V (VOVP-TH 0.9 V to 1.1 V) the NMOS is turned off. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ISSI Integrated Silicon Solution |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC to GND |  | -0.3 |  | 6 | V |  | 3 |
| CS, ADJ, GATE, TOFF, OVP, FB voltage |  | -0.3 |  | 6 | V |  | 3 |
| VCC maximum input current |  |  |  | 10 | mA |  | 3 |
| Junction temperature range |  | -40 |  | 150 | °C |  | 3 |
| Storage temperature range |  | -65 |  | 150 | °C |  | 3 |
| ESD human body model |  |  |  | 3500 | V |  | 3 |
| Operating temperature range (ordering info SN3948ID08E, industrial grade) |  | -40 |  | 85 | °C |  | 2 |
| Input voltage range | VINDC | 5 |  | 100 | V | external resistor between supply and VCC pin (note 2) | 3 |
| VCC clamp voltage | VCC | 4.4 | 5 | 5.6 | V | Rin=10K | 3 |
| Undervoltage lockout threshold (VCC rising) | UVLO | 2 | 2.7 | 3 | V | VCC rising | 3 |
| Quiescent supply current | ISS |  | 250 | 400 | uA | VCC=5V | 3 |
| Quiescent current during chip undervoltage |  |  | 50 | 75 | uA | VCC=2.5V | 3 |
| Input peak current detection threshold | VCSTH | 215 | 240 | 265 | mV | ADJ=5V | 3 |
| Feedback threshold (output current) | VfbTH | 0.29 | 0.3 | 0.31 | V |  | 3 |
| Overvoltage protection threshold | VOVP-TH | 0.9 | 1 | 1.1 | V |  | 3 |
| Input current sense blanking time | TBLANK |  | 500 |  | ns | VCS=VCSTH+50mV | 3 |
| Minimum constant off time | TOFF |  | 10 |  | µs | Rext=250KΩ | 3 |
| Peak current control low threshold | VADJ |  | 0.5 |  | V |  | 3 |
| Peak current control high threshold | VADJ |  | 2.4 |  | V |  | 3 |
| Overtemperature protection threshold | TSD |  | 150 |  | °C |  | 3 |
| Overtemperature protection hysteresis | TSD-HYS |  | 20 |  | °C |  | 3 |
| Undervoltage lockout hysteresis | ΔUVLO |  | 300 |  | mV |  | 3 |

## CAD (KiCad official)

- Symbol: `SN3948`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `sn3948-etched.step` / `sn3948-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn3948.step` / `sn3948.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ISSI Integrated Silicon Solution datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589838754354794496) (13 pp, sha256 `01443d38f21bc0fb`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn3948-datasheet.pdf)