# SM8082AAAC

**Silergy Corp** · DC-DC Converters · SOT-23-5

SM8082AAAC from Silergy Corp, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable control input. Pull high (VEN,H ≥ 1.2V) to turn the regulator on; drive low (VEN,L ≤ 0.4V) to shut down (shutdown current 0.1µA typ). Do not leave floating; add a 1MΩ pull-down to GND when the driving source can be high-Z. |
| 2 | GND | power_in | Ground return pin for the IC and the internal low-side synchronous FET. Maximize copper connection to GND plane for best thermal and noise performance. |
| 3 | LX | output | Switching-node output of the internal power stage. Connect to the external inductor (typ. 1.0µH). PCB copper area on this net must be minimized to avoid noise coupling. Absolute LX range -0.3V to 6.0V (tested to -3V/+7V for <40ns transients). |
| 4 | IN | power_in | Power supply input, 2.5V to 5.5V operating range (absolute max 6.0V). Decouple to GND with at least a 10µF X5R ceramic capacitor placed close to the IN/GND pins to minimize loop area. |
| 5 | FB | input | Output voltage feedback pin. Connect to the mid-point of the output resistor divider (RH from VOUT to FB, RL from FB to GND) to program VOUT = 0.6 × (1 + RH/RL). Internal reference VREF = 0.6V (588-612mV). Keep this trace away from LX to avoid noise pickup. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | SOT-23-5 |
| Category | PMIC |
| Pins | 5 |

## Ordering variants

Same part, different packaging or reel option.

- `SM8082AAAC`

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.5 |  | 5.5 | V |  | 4 |
| Quiescent Current | IQ |  | 70 | 100 | µA | VFB=VREF×105% | 4 |
| Shutdown Current | ISHDN |  | 0.1 | 1 | µA | VEN=0V | 4 |
| Feedback Reference Voltage | VREF | 588 | 600 | 612 | mV | IOUT=0.5A, CCM | 4 |
| FB, EN Voltage |  | -0.3 |  |  | V |  | 3 |
| LX Voltage |  | -0.3 |  | 6 | V | *1 tested down to -3V <40ns; *2 tested up to +7V <40ns | 3 |
| Supply Input Voltage |  | -0.3 |  | 6 | V |  | 3 |
| Junction Temperature Range |  | -40 |  | 150 | °C |  | 3 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 3 |
| Supply Input Voltage |  | 2.5 |  | 5.5 | V |  | 3 |
| Junction Temperature Range |  | -40 |  | 125 | °C |  | 3 |
| Ambient Temperature Range |  | -40 |  | 85 | °C |  | 3 |
| Input UVLO Threshold | VUVLO |  | 2.5 |  | V |  | 4 |
| Input UVLO Hysteresis | VHYS |  | 150 |  | mV |  | 4 |
| LX Node Discharge Resistance | RDIS |  | 50 |  | Ω |  | 4 |
| Top FET RON | RDS(ON)1 |  | 130 |  | mΩ |  | 4 |
| Bottom FET RON | RDS(ON)2 |  | 90 |  | mΩ |  | 4 |
| EN Input Voltage High | VEN,H |  | 1.2 |  | V |  | 4 |
| EN Input Voltage Low | VEN,L |  | 0.4 |  | V |  | 4 |
| Min on Time | tON,MIN |  | 60 |  | ns |  | 4 |
| Maximum Duty Cycle | DMAX |  | 100 |  | % |  | 4 |
| Turn on Delay | tON,DLY |  | 0.5 |  | ms | from EN high to LX start switching | 4 |
| Soft-start Time | tSS |  | 1 |  | ms | VOUT from 0% to 100% | 4 |
| Switching Frequency | fSW |  | 1.5 |  | MHz | IOUT=0.5A, CCM | 4 |
| Top FET Current Limit | ILMT,TOP |  | 3.5 |  | A |  | 4 |
| Thermal Shutdown Temperature | TSD |  | 150 |  | °C |  | 4 |
| Thermal Shutdown Hysteresis | THYS |  | 20 |  | °C |  | 4 |
| Power Dissipation | PD |  | 0.83 |  | W | TA = 25°C | 3 |
| Package Thermal Resistance, junction-to-ambient | θJA |  | 120 |  | °C/W | natural convection, TA = 25°C, 2OZ two-layer evaluation board (Note 2) | 3 |
| Package Thermal Resistance, junction-to-case | θJC |  | 20 |  | °C/W |  | 3 |
| Lead Temperature (Soldering) |  |  | 260 |  | °C | 10 sec soldering | 3 |

## CAD (KiCad official)

- Symbol: `SM8082AAAC`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `sm8082aaac-etched.step` / `sm8082aaac-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sm8082aaac.step` / `sm8082aaac.glb` are the bare package body.

## 3D model downloads

Two STEP files. Same geometry, different body top:

| File | Size | Use it when |
|---|---|---|
| [`sm8082aaac.step`](sm8082aaac.step) | 85 KB | You want the bare part, or you mark your own boards. |
| [`sm8082aaac-etched.step`](sm8082aaac-etched.step) | 2.1 MB | You want the part with `SM8082AAAC` already on it. |

The marking in the etched file is real recessed geometry cut into the solid, not a
texture or a decal: 514 faces against 102 in the bare model. It
survives export, section views, and rendering in any CAD tool, and it drops straight
into KiCad or Fusion with no extra setup.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Silergy Corp datasheet](docs/sm8082aaac-datasheet.pdf) (10 pp, sha256 `3d1af3cb0c77bf0a`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sm8082aaac-datasheet.pdf)