SM74HC595D

{
  "schema_version": 1,
  "type": "component",
  "slug": "sm74hc595d",
  "title": "SM74HC595D",
  "brief": "Shenzhen Sunmoon Micro Shifting Register, SOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "sm74hc595d"
  ],
  "component": {
    "mpn": "SM74HC595D",
    "manufacturer": "Shenzhen Sunmoon Micro",
    "package": "SOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shifting Register",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/60b63267e84d48edb15919eee5d46019.pdf",
    "parts": {
      "symbol": "sm74hc595d.kicad_sym",
      "footprint": "sm74hc595d.kicad_mod",
      "model_3d": "sm74hc595d-etched.glb",
      "model_3d_plain": "sm74hc595d.glb",
      "model_3d_step": "sm74hc595d-etched.step",
      "model_3d_step_plain": "sm74hc595d.step",
      "lbr": "sm74hc595d.lbr"
    },
    "distributor_links": {
      "lcsc": "C93838"
    },
    "pins": [
      {
        "number": "1",
        "name": "Q1",
        "type": "tri_state",
        "description": "Parallel latched output bit 1 from the storage register. Three-state; enabled when /G (pin 13) is low."
      },
      {
        "number": "2",
        "name": "Q2",
        "type": "tri_state",
        "description": "Parallel latched output bit 2. Three-state, enabled by /G low."
      },
      {
        "number": "3",
        "name": "Q3",
        "type": "tri_state",
        "description": "Parallel latched output bit 3. Three-state, enabled by /G low."
      },
      {
        "number": "4",
        "name": "Q4",
        "type": "tri_state",
        "description": "Parallel latched output bit 4. Three-state, enabled by /G low."
      },
      {
        "number": "5",
        "name": "Q5",
        "type": "tri_state",
        "description": "Parallel latched output bit 5. Three-state, enabled by /G low."
      },
      {
        "number": "6",
        "name": "Q6",
        "type": "tri_state",
        "description": "Parallel latched output bit 6. Three-state, enabled by /G low."
      },
      {
        "number": "7",
        "name": "Q7",
        "type": "tri_state",
        "description": "Parallel latched output bit 7 (MSB of the 8-bit output). Three-state, enabled by /G low."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Logic ground reference (0 V)."
      },
      {
        "number": "9",
        "name": "Q7'",
        "type": "output",
        "description": "Serial data output from the last stage of the shift register. Used to daisy-chain multiple 74HC595 devices; not three-state."
      },
      {
        "number": "10",
        "name": "/SCLR",
        "type": "input",
        "description": "Active-low asynchronous shift-register clear. Driving low forces all shift-register bits to 0 (Q7' = 0); does not affect the storage latch until an RCK edge."
      },
      {
        "number": "11",
        "name": "SCK",
        "type": "input",
        "description": "Shift-register clock. Data on SER is shifted into the shift register on the rising edge. Max 50 MHz (typ. 52 MHz at Vcc = 4.5 V)."
      },
      {
        "number": "12",
        "name": "RCK",
        "type": "input",
        "description": "Storage/latch register clock. On the rising edge, the shift-register contents are transferred to the output storage register (latched to Q0-Q7)."
      },
      {
        "number": "13",
        "name": "/G",
        "type": "input",
        "description": "Active-low output enable for the parallel outputs Q0-Q7. Low enables the latched data onto the outputs; high places Q0-Q7 in high-impedance (3-state)."
      },
      {
        "number": "14",
        "name": "SER",
        "type": "input",
        "description": "Serial data input to the shift register. Sampled on the rising edge of SCK; tSU ≈ 16 ns, tH ≈ 3 ns."
      },
      {
        "number": "15",
        "name": "Q0",
        "type": "tri_state",
        "description": "Parallel latched output bit 0 (LSB of the 8-bit output). Three-state, enabled by /G low."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage, 2.0 V to 6.0 V. Bypass with 100 nF near the pin."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/60b63267e84d48edb15919eee5d46019.pdf",
        "pages": 7,
        "sha256": "a82a24e37bce2202",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -4.445
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "74HC595",
      "logic_family": "74HC",
      "function_code": "595",
      "function_class": "ShiftRegister",
      "function_name": "8-Bit SIPO Shift Register with Output Latch",
      "manufacturer": "Sunmoon Micro (Shenzhen)",
      "is_specialty": false
    },
    "models_3d": [
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sm74hc595d-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "8731dfc02cab9b7a163b4247f37af1cd76c69233b7fabcaa09704af26fcfc3ca",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Shenzhen Sunmoon Micro",
      "Package": "SOP-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "sm74hc595d"
  ],
  "discovery_pitch": "SM74HC595D (Shenzhen Sunmoon Micro) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "sm74hc595d.kicad_sym",
    "sm74hc595d.kicad_mod",
    "sm74hc595d.glb",
    "sm74hc595d.step",
    "sm74hc595d-etched.step",
    "sm74hc595d.lbr",
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    "docs/sm74hc595d-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "SM74HC595DD",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-25T06:17:50.221Z"
}