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SLVU2.8-4-TP
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TECH PUBLIC ESD Protection Devices, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SLVU2.8-4-TP
TECH PUBLIC · ESD Protection Devices · SO-8
SLVU2.8-4-TP from TECH PUBLIC, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1 | passive | TVS diode terminal on the left upper channel, paired with pin 2 in the schematic and tied with pin 8 in the capacitance test (pins 1,8 to 2,7). |
| 2 | 2 | passive | TVS diode terminal on the left upper channel, paired with pin 1 in the schematic and tied with pin 7 in the capacitance test (pins 1,8 to 2,7). |
| 3 | 3 | passive | TVS diode terminal on the left lower channel, paired with pin 4 in the schematic and tied with pin 6 in the capacitance test (pins 3,6 to 4,5). |
| 4 | 4 | passive | TVS diode terminal on the left lower channel, paired with pin 3 in the schematic and tied with pin 5 in the capacitance test (pins 3,6 to 4,5). |
| 5 | 5 | passive | TVS diode terminal on the right lower channel, paired with pin 6 in the schematic and tied with pin 4 in the capacitance test (pins 3,6 to 4,5). |
| 6 | 6 | passive | TVS diode terminal on the right lower channel, paired with pin 5 in the schematic and tied with pin 3 in the capacitance test (pins 3,6 to 4,5). |
| 7 | 7 | passive | TVS diode terminal on the right upper channel, paired with pin 8 in the schematic and tied with pin 2 in the capacitance test (pins 1,8 to 2,7). |
| 8 | 8 | passive | TVS diode terminal on the right upper channel, paired with pin 7 in the schematic and tied with pin 1 in the capacitance test (pins 1,8 to 2,7). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SO-8 |
| Category | Circuit Protection |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
SLVU2.8-4-TP - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
slvu2-8-4-tp-etched.step/slvu2-8-4-tp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);slvu2-8-4-tp.step/slvu2-8-4-tp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TECH PUBLIC datasheet (4 pp, sha256
27282a5734256b54, retrieved 2026-11-04, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SLVU2.8-4-TP
**TECH PUBLIC** · ESD Protection Devices · SO-8
SLVU2.8-4-TP from TECH PUBLIC, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1 | passive | TVS diode terminal on the left upper channel, paired with pin 2 in the schematic and tied with pin 8 in the capacitance test (pins 1,8 to 2,7). |
| 2 | 2 | passive | TVS diode terminal on the left upper channel, paired with pin 1 in the schematic and tied with pin 7 in the capacitance test (pins 1,8 to 2,7). |
| 3 | 3 | passive | TVS diode terminal on the left lower channel, paired with pin 4 in the schematic and tied with pin 6 in the capacitance test (pins 3,6 to 4,5). |
| 4 | 4 | passive | TVS diode terminal on the left lower channel, paired with pin 3 in the schematic and tied with pin 5 in the capacitance test (pins 3,6 to 4,5). |
| 5 | 5 | passive | TVS diode terminal on the right lower channel, paired with pin 6 in the schematic and tied with pin 4 in the capacitance test (pins 3,6 to 4,5). |
| 6 | 6 | passive | TVS diode terminal on the right lower channel, paired with pin 5 in the schematic and tied with pin 3 in the capacitance test (pins 3,6 to 4,5). |
| 7 | 7 | passive | TVS diode terminal on the right upper channel, paired with pin 8 in the schematic and tied with pin 2 in the capacitance test (pins 1,8 to 2,7). |
| 8 | 8 | passive | TVS diode terminal on the right upper channel, paired with pin 7 in the schematic and tied with pin 1 in the capacitance test (pins 1,8 to 2,7). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SO-8 |
| Category | Circuit Protection |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `SLVU2.8-4-TP`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `slvu2-8-4-tp-etched.step` / `slvu2-8-4-tp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `slvu2-8-4-tp.step` / `slvu2-8-4-tp.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TECH PUBLIC datasheet](docs/slvu2-8-4-tp-datasheet.pdf) (4 pp, sha256 `27282a5734256b54`, retrieved 2026-11-04, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/slvu2-8-4-tp-datasheet.pdf)