component
SLM7888CH
Public Made by Adomby adom
Sillumin Gate Drive ICs, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 2d ago |
| viewers | 2d ago |
| package.json | 2d ago |
| page.json | 2d ago |
| README.md | 2d ago |
| slm7888ch-etched.glb | 2d ago |
| slm7888ch-etched.step | 2d ago |
| slm7888ch-hero.glb | 2d ago |
| slm7888ch-hero.overlay.json | 2d ago |
| slm7888ch.glb | 2d ago |
| slm7888ch.kicad_mod | 2d ago |
| slm7888ch.kicad_sym | 2d ago |
| slm7888ch.lbr | 2d ago |
| slm7888ch.step | 2d ago |
| verification.json | 2d ago |
SLM7888CH
Sillumin · Gate Drive ICs · SOIC-20-300mil
SLM7888CH from Sillumin, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HIN1 | input | Logic input for high-side gate driver output HO1; a logic 1 requires VIH of at least 2.5 V and a logic 0 requires VIL of at most 1.0 V. |
| 2 | LIN1 | input | Logic input for low-side gate driver output LO1; a logic 1 requires VIH of at least 2.5 V and a logic 0 requires VIL of at most 1.0 V. |
| 3 | HIN2 | input | Logic input for high-side gate driver output HO2; a logic 1 requires VIH of at least 2.5 V and a logic 0 requires VIL of at most 1.0 V. |
| 4 | LIN2 | input | Logic input for low-side gate driver output LO2; a logic 1 requires VIH of at least 2.5 V and a logic 0 requires VIL of at most 1.0 V. |
| 5 | HIN3 | input | Logic input for high-side gate driver output HO3; a logic 1 requires VIH of at least 2.5 V and a logic 0 requires VIL of at most 1.0 V. |
| 6 | LIN3 | input | Logic input for low-side gate driver output LO3; a logic 1 requires VIH of at least 2.5 V and a logic 0 requires VIL of at most 1.0 V. |
| 7 | LO3 | output | Low-side gate driver output for phase 3, referenced to GND and operating between GND and VDD. |
| 8 | VS3 | power_in | High-side floating supply offset for phase 3, rated from -0.3 V to 160 V with respect to GND. |
| 9 | HO3 | output | High-side gate driver output for phase 3, referenced to VS3 and operating between VS3 and VB3. |
| 10 | VB3 | power_in | High-side floating supply for phase 3, which must be held 10 V to 20 V above VS3. |
| 11 | GND | power_in | Ground reference for logic inputs and low-side gate drivers; all voltage parameters are referenced to this pin. |
| 12 | VDD | power_in | Logic and all low-side gate driver power supply, specified from 10 V to 20 V. |
| 13 | LO2 | output | Low-side gate driver output for phase 2, referenced to GND and operating between GND and VDD. |
| 14 | VS2 | power_in | High-side floating supply offset for phase 2, rated from -0.3 V to 160 V with respect to GND. |
| 15 | HO2 | output | High-side gate driver output for phase 2, referenced to VS2 and operating between VS2 and VB2. |
| 16 | VB2 | power_in | High-side floating supply for phase 2, which must be held 10 V to 20 V above VS2. |
| 17 | LO1 | output | Low-side gate driver output for phase 1, referenced to GND and operating between GND and VDD. |
| 18 | VS1 | power_in | High-side floating supply offset for phase 1, rated from -0.3 V to 160 V with respect to GND. |
| 19 | HO1 | output | High-side gate driver output for phase 1, referenced to VS1 and operating between VS1 and VB1. |
| 20 | VB1 | power_in | High-side floating supply for phase 1, which must be held 10 V to 20 V above VS1. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Sillumin |
| Package | SOIC-20-300mil |
| Category | Power Management ICs |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-side floating absolute voltage | VB | -0.3 | 185 | V | 4 | ||
| Low-side and logic fixed supply voltage | VCC | -0.3 | 25 | V | 4 | ||
| Allowable offset supply voltage transient | dVS/dt | 50 | V/ns | 4 | |||
| Package power dissipation (SOP20W) | PD | 1.5 | W | TA ≤ +25°C | 4 | ||
| Thermal resistance, junction to ambient (SOP20W) | θJA | 60 | °C/W | SOP20W, board mounted, still air | 4 | ||
| Junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | TS | -55 | 150 | °C | 4 | ||
| Lead temperature (soldering, 10 seconds) | TL | 300 | °C | 10 seconds soldering | 4 | ||
| High-side floating supply offset voltage | VS | -0.3 | 160 | V | Tested with VDD=15V | 4 | |
| Low-side and logic fixed supply voltage | VDD | 10 | 20 | V | 4 | ||
| Ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Turn-on propagation delay | ton | 100 | 220 | ns | VS = 0 V | 5 | |
| Turn-off propagation delay | toff | 110 | 240 | ns | VS = 0 V | 5 | |
| Turn-on rise time | tr | 50 | 120 | ns | 5 | ||
| Turn-off fall time | tf | 30 | 80 | ns | 5 | ||
| Deadtime, LS turn-off to HS turn-on & HS turn-on to LS turn-off | DT | 100 | 270 | 440 | ns | VIN = 0 V & 5 V | 5 |
| Matching delay, HS & LS turn-on/off | MT | 10 | 50 | ns | 5 | ||
| Matching delay, Dead Time | MDT | 45 | 80 | ns | 5 | ||
| Logic “1” input voltage (LIN, HIN) | VIH | 2.5 | V | VCC = 10 V to 20V | 5 | ||
| Logic “0” input voltage (LIN, HIN) | VIL | 1 | V | 5 | |||
| High level output voltage, VBIAS - VO | VOH | 0.35 | 0.5 | V | IO = 20 mA | 5 | |
| Low level output voltage, VO | VOL | 0.1 | 0.2 | V | 5 | ||
| VDD supply undervoltage positive going threshold | VDDUV+ | 5.5 | 6.6 | 7.8 | V | 5 | |
| VDD supply undervoltage negative going threshold | VDDUV- | 5.2 | 6.3 | 7.5 | V | 5 | |
| VDD supply undervoltage lockout hysteresis | VDDUVH | 0.3 | V | 5 | |||
| VBS supply undervoltage positive going threshold | VBSUV+ | 5.2 | 6.2 | 7.2 | V | 5 | |
| VBS supply undervoltage negative going threshold | VBSUV- | 4.9 | 5.9 | 6.9 | V | 5 | |
| VBS supply undervoltage lockout hysteresis | VBSUVH | 0.3 | V | 5 | |||
| Offset supply leakage current | ILK | 10 | µA | VB1,2,3 = VS1,2,3 = 160 V | 5 | ||
| Quiescent VBS supply current | IQBS | 70 | 100 | µA | VIN = 0 V | 5 | |
| Quiescent VDD supply current | IQDD | 400 | 500 | µA | 5 | ||
| Operating VDD supply current for each channel | IOPDD | 560 | 900 | µA | fLIN1,2,3 = 20 kHz | 5 | |
| Operating VBS supply current for each channel | IOPBS | 200 | 400 | µA | fLIN1,2,3 = 20 kHz | 5 | |
| Logic “1” input bias current | IIN+ | 25 | 40 | µA | HIN1, 2, 3 = 5 V, LIN1, 2, 3 = 5 V | 6 | |
| Logic “0” input bias current | IIN- | 2 | µA | HIN1, 2, 3 = 0 V, LIN1, 2, 3 = 0 V | 6 | ||
| Input pull-down resistance | RIN | 150 | 200 | 300 | kΩ | 6 | |
| Output high short circuit pulsed current | IO+ | 350 | mA | VO = 0 V, VIN = VIH, PW ≤ 10 µs | 6 | ||
| Output low short circuit pulsed current | IO- | 650 | mA | VO = 15 V, VIN = VIL, PW ≤ 10 µs | 6 |
CAD (KiCad official)
- Symbol:
SLM7888CH - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
slm7888ch-etched.step/slm7888ch-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);slm7888ch.step/slm7888ch.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Sillumin datasheet (13 pp, sha256
e6f6846c75ee4da9, retrieved 2026-11-05, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).