component
SLM6240AB-13GTR
Public Made by Adomby adom
Sillumin DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SLM6240AB-13GTR
Sillumin · DC-DC Converters · SOIC-8-EP
SLM6240AB-13GTR from Sillumin, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Power ground for the switching power stage, connected to the system ground. |
| 2 | IN | power_in | Supply input with an operating voltage range of 2.7 V to 5.5 V. |
| 3 | EN | input | Enable control: a logic high (VIH min 1.4 V) enables the IC and a logic low (VIL max 0.4 V) disables it, and it must not be left floating, so connect it to IN when unused. |
| 4 | COMP | passive | Error amplifier compensation node used for external loop compensation. |
| 5 | AGND | power_in | Analog ground for the control circuitry. |
| 6 | FB | input | Feedback input, connected to a resistor divider from the output to set VOUT; FB is regulated to 1.262 V (VFB 1.23 V to 1.29 V). |
| 7 | SS | input | Soft-start control input, where a capacitor to ground sets the soft-start duration (10 nF in the application example), SS is discharged in shutdown, and it may be left unconnected. |
| 8 | SW | output | Switch output connected to the inductor and Schottky diode; keep the trace to the input bypass capacitor short to minimize EMI. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Sillumin |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage operation range | VIN | 2.7 | 5.5 | V | 4 | ||
| SW to Ground voltage | -0.3 | 28 | V | SW to Ground | 4 | ||
| VIN, EN, FB, SS, COMP to Ground voltage | -0.3 | 6.5 | V | VIN, EN, FB, SS, COMP to Ground | 4 | ||
| Total power dissipation | PTOT | 1.5 | w | TS ≤100°C | 4 | ||
| Maximum junction temperature | TJMAX | 150 | °C | 4 | |||
| Storage temperature range | TSTG | -65 | 150 | °C | 4 | ||
| Operating temperature range | TA | -40 | 125 | °C | 4 | ||
| Latch-up | -100 | 100 | mA | 4 | |||
| ESD (HBM) | 2000 | V | HBM | 4 | |||
| ESD (CDM) | 200 | V | CDM | 4 | |||
| ESD (FICDM) | 1500 | V | FICDM | 4 | |||
| Feedback voltage | VFB | 1.23 | 1.26 | 1.29 | V | 4 | |
| Soft start pin bias current | ISS | 2 | 4.5 | 7 | uA | VSS=1.2V | 4 |
| Switching peak current limit | ICL | 3.5 | 4 | A | VIN=3.6V, Duty cycle = 70% | 4 | |
| Maximum duty cycle | DC | 90 | % | 4 | |||
| EN pin logic high | VIH | 1.4 | V | 4 | |||
| EN pin logic low | VIL | 0.4 | V | 4 | |||
| Chip quiescent current (non-switching) | IQ | 0.3 | 0.35 | mA | VIN=3.6V, VFB=1.4V, Non-switching | 4 | |
| Chip quiescent current (switching) | IQ | 3 | 5 | mA | VIN=3.6V, VFB=1.0V, Switching | 4 | |
| Supply current in shutdown | ISHDN | 0.1 | 1 | uA | EN=GND | 4 | |
| Feedback voltage line regulation | LNR | 0.05 | 0.15 | %/V | VFB from 2.7V to 5.5V | 4 | |
| Feedback input current | IFB | 0 | 80 | nA | 4 | ||
| Under voltage lockout threshold | UVLO | 2.5 | V | VIN Rising | 4 | ||
| Under voltage lockout hysteresis | 200 | mV | 4 | ||||
| Switching frequency | fREQ | 800 | kHz | 4 | |||
| Switching ON resistance | RDSON | 80 | mΩ | VIN=3.6V, VSW=12V, Duty cycle = 70% | 4 | ||
| Switch leakage current | ISW | 15 | uA | VSW=12V, EN=GND | 4 | ||
| EN pull down resistor | REN | 1 | MΩ | 4 | |||
| Thermal shutdown temperature | TSD | 150 | °C | 4 | |||
| Thermal shutdown hysteresis | TSD_HYS | 15 | °C | 4 | |||
| Junction to Ambient thermal resistance | Rth-JA | 60 | °C/w | 4 | |||
| Junction to Case thermal resistance | Rth-JC | 15 | °C/w | 4 |
CAD (KiCad official)
- Symbol:
SLM6240AB-13GTR - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
slm6240ab-13gtr-etched.step/slm6240ab-13gtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);slm6240ab-13gtr.step/slm6240ab-13gtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Sillumin datasheet (8 pp, sha256
2e822aee93c4cde4, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SLM6240AB-13GTR
**Sillumin** · DC-DC Converters · SOIC-8-EP
SLM6240AB-13GTR from Sillumin, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Power ground for the switching power stage, connected to the system ground. |
| 2 | IN | power_in | Supply input with an operating voltage range of 2.7 V to 5.5 V. |
| 3 | EN | input | Enable control: a logic high (VIH min 1.4 V) enables the IC and a logic low (VIL max 0.4 V) disables it, and it must not be left floating, so connect it to IN when unused. |
| 4 | COMP | passive | Error amplifier compensation node used for external loop compensation. |
| 5 | AGND | power_in | Analog ground for the control circuitry. |
| 6 | FB | input | Feedback input, connected to a resistor divider from the output to set VOUT; FB is regulated to 1.262 V (VFB 1.23 V to 1.29 V). |
| 7 | SS | input | Soft-start control input, where a capacitor to ground sets the soft-start duration (10 nF in the application example), SS is discharged in shutdown, and it may be left unconnected. |
| 8 | SW | output | Switch output connected to the inductor and Schottky diode; keep the trace to the input bypass capacitor short to minimize EMI. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Sillumin |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage operation range | VIN | 2.7 | | 5.5 | V | | 4 |
| SW to Ground voltage | | -0.3 | | 28 | V | SW to Ground | 4 |
| VIN, EN, FB, SS, COMP to Ground voltage | | -0.3 | | 6.5 | V | VIN, EN, FB, SS, COMP to Ground | 4 |
| Total power dissipation | PTOT | | | 1.5 | w | TS ≤100°C | 4 |
| Maximum junction temperature | TJMAX | | | 150 | °C | | 4 |
| Storage temperature range | TSTG | -65 | | 150 | °C | | 4 |
| Operating temperature range | TA | -40 | | 125 | °C | | 4 |
| Latch-up | | -100 | | 100 | mA | | 4 |
| ESD (HBM) | | | | 2000 | V | HBM | 4 |
| ESD (CDM) | | | | 200 | V | CDM | 4 |
| ESD (FICDM) | | | | 1500 | V | FICDM | 4 |
| Feedback voltage | VFB | 1.23 | 1.26 | 1.29 | V | | 4 |
| Soft start pin bias current | ISS | 2 | 4.5 | 7 | uA | VSS=1.2V | 4 |
| Switching peak current limit | ICL | 3.5 | | 4 | A | VIN=3.6V, Duty cycle = 70% | 4 |
| Maximum duty cycle | DC | | | 90 | % | | 4 |
| EN pin logic high | VIH | 1.4 | | | V | | 4 |
| EN pin logic low | VIL | | | 0.4 | V | | 4 |
| Chip quiescent current (non-switching) | IQ | | 0.3 | 0.35 | mA | VIN=3.6V, VFB=1.4V, Non-switching | 4 |
| Chip quiescent current (switching) | IQ | | 3 | 5 | mA | VIN=3.6V, VFB=1.0V, Switching | 4 |
| Supply current in shutdown | ISHDN | | 0.1 | 1 | uA | EN=GND | 4 |
| Feedback voltage line regulation | LNR | | 0.05 | 0.15 | %/V | VFB from 2.7V to 5.5V | 4 |
| Feedback input current | IFB | | 0 | 80 | nA | | 4 |
| Under voltage lockout threshold | UVLO | | 2.5 | | V | VIN Rising | 4 |
| Under voltage lockout hysteresis | | | 200 | | mV | | 4 |
| Switching frequency | fREQ | | 800 | | kHz | | 4 |
| Switching ON resistance | RDSON | | 80 | | mΩ | VIN=3.6V, VSW=12V, Duty cycle = 70% | 4 |
| Switch leakage current | ISW | | 15 | | uA | VSW=12V, EN=GND | 4 |
| EN pull down resistor | REN | | 1 | | MΩ | | 4 |
| Thermal shutdown temperature | TSD | | 150 | | °C | | 4 |
| Thermal shutdown hysteresis | TSD_HYS | | 15 | | °C | | 4 |
| Junction to Ambient thermal resistance | Rth-JA | | 60 | | °C/w | | 4 |
| Junction to Case thermal resistance | Rth-JC | | 15 | | °C/w | | 4 |
## CAD (KiCad official)
- Symbol: `SLM6240AB-13GTR`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files: `slm6240ab-13gtr-etched.step` / `slm6240ab-13gtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `slm6240ab-13gtr.step` / `slm6240ab-13gtr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Sillumin datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589836147233742848) (8 pp, sha256 `2e822aee93c4cde4`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/slm6240ab-13gtr-datasheet.pdf)