component
SLM5418EJ-7G
Public Made by Adomby adom
Sillumin DC-DC Converters, QFN-10(1.4x1.8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 11d ago |
| viewers | 11d ago |
| package.json | 11d ago |
| page.json | 11d ago |
| README.md | 11d ago |
| slm5418ej-7g-etched.glb | 11d ago |
| slm5418ej-7g-etched.step | 11d ago |
| slm5418ej-7g-hero.glb | 11d ago |
| slm5418ej-7g-hero.overlay.json | 11d ago |
| slm5418ej-7g.glb | 11d ago |
| slm5418ej-7g.kicad_mod | 11d ago |
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| slm5418ej-7g.lbr | 11d ago |
| slm5418ej-7g.step | 11d ago |
SLM5418EJ-7G
Sillumin · DC-DC Converters · QFN-10(1.4x1.8)
SLM5418EJ-7G from Sillumin, in a QFN-10(1.4x1.8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Power ground. |
| 2 | EN | input | Enable input; set high (above about 0.9V) to enable the device, floating or pulled low disables it, with an internal 1MΩ resistor to ground. |
| 3 | CTL | input | Analog input voltage; the VOUT2 voltage will be -1x the CTL pin voltage. |
| 4 | NC | unconnected | No connect; leave this pin open. |
| 5 | VOUT2 | power_out | Negative linear regulator output (0V to VOUT1, up to 240mA typical current limit); a decoupling capacitor is needed. |
| 6 | GND | power_in | Power ground. |
| 7 | VOUT1 | power_out | Negative charge pump output (equal to -VIN unregulated); a decoupling capacitor is needed. |
| 8 | CN | passive | Negative terminal of the fly capacitor. |
| 9 | CP | passive | Positive terminal of the fly capacitor. |
| 10 | IN | power_in | Input power supply pin (2.3V to 5.5V); a decoupling capacitor is needed to prevent large voltage spikes at the input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Sillumin |
| Package | QFN-10(1.4x1.8) |
| Category | Power Management |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VIN | -0.3 | 6 | V | 2 | ||
| All Other Pins | -0.3 | 6 | V | 2 | |||
| Junction Temperature | TJ | 150 | °C | 2 | |||
| Lead Temperature | 260 | °C | 2 | ||||
| Continuous Power Dissipation | PD | 1.47 | W | TA = +25°C | 2 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 2 | ||
| Thermal Resistance junction-ambient | θJA | 140 | °C/W | QFN-10(1.4mmx1.8mm), JESD51-7 | 2 | ||
| Thermal Resistance junction-case | θJC | 30 | °C/W | QFN-10(1.4mmx1.8mm), JESD51-7 | 2 | ||
| VIN Range | VIN | 2.3 | 5.5 | V | 4 | ||
| Supply current (shutdown) | ISD | 2 | uA | VEN =0V, VIN=3.3V | 4 | ||
| Supply current (switching) | 2.8 | mA | VEN =3.3V, no load, TJ=+25°C | 4 | |||
| Supply current (switching) | 3.3 | mA | VEN =3.3V, no load, TJ > -40°C & TJ < +125°C | 4 | |||
| Output discharge resistor | RDIS1 | 170 | 310 | Ω | VEN=0V, VOUT1 rail | 4 | |
| Output discharge resistor | RDIS2 | 80 | 160 | Ω | VEN =0V, VOUT2 rail | 4 | |
| Output accuracy | 1 | % | Compared with CTL voltage, room temp, IOUT2=10mA | 4 | |||
| Output accuracy | 2 | % | Over temp , IOUT2=10mA | 4 | |||
| Output offset | 20 | mV | IOUT2=10mA | 4 | |||
| EN input current | 2 | uA | VEN =2V | 4 | |||
| Under-voltage lockout threshold rising | UVLO | 2.2 | V | 4 | |||
| Under-voltage lockout threshold Hysteresis | 0.15 | V | 4 | ||||
| Charge pump frequency | Fsw | 1 | MHz | 4 | |||
| Charge pump equivalent output resistance | RON | 0.134 | Ω | VIN=3.3V, IOUT1=100mA | 4 | ||
| Charge pump current limit | 2 | A | 4 | ||||
| Load current limit | 240 | mA | VIN=3.3V, VOUT2=-2.5V | 4 | |||
| Dropout voltage | VDROP | 20 | mV | VIN=2.7V, IOUT2=60mA | 4 | ||
| Dropout voltage | VDROP | 15 | mV | VIN =3.3V, IOUT2=60mA | 4 | ||
| Load regulation | 0.005 | %/mA | VOUT1=-3.3V, CTL=1V | 4 | |||
| PSRR | PSRR | 60 | dB | 100Hz, COUT1=1uF COUT2=1uF, IOUT2=10mA | 4 | ||
| PSRR | PSRR | 50 | dB | 50kHz, COUT1=1uF, COUT2=1uF, IOUT2=10mA | 4 | ||
| PSRR | PSRR | 40 | dB | 300kHz, COUT1=1uF, COUT2=1uF, IOUT2=10mA | 4 | ||
| Soft-start slew-rate | 5 | V/ms | 4 | ||||
| EN turn-on delay | 200 | us | 4 | ||||
| EN input logic low voltage | VIH | 0.71 | V | 4 | |||
| EN input logic high voltage | VIL | 0.91 | V | 4 | |||
| Thermal shutdown | 160 | °C | 4 | ||||
| Thermal hysteresis | 25 | °C | 4 | ||||
| Output ripple OUT1 | VRipple_OUT1 | 8 | mV | VIN=3.3V, VOUT1=-3.3V, CFLY=COUT1=4.7uF, IOUT1=60mA | 4 | ||
| Output ripple OUT2 | VRipple_OUT2 | 1 | mV | VIN=3.3V, VOUT2=2.5V, COUT2=1uF, IOUT2=60mA | 4 |
CAD (KiCad official)
- Symbol:
SLM5418EJ-7G - Footprint:
Package_DFN_QFN:UQFN-10_1.4x1.8mm_P0.4mm - 3D model: QFN-10(1.4x1.8) (KiCad packages3D, STEP)
- 3D model files:
slm5418ej-7g-etched.step/slm5418ej-7g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);slm5418ej-7g.step/slm5418ej-7g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Sillumin datasheet (9 pp, sha256
0de4b24472b3dbec, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).