component
SLM27211CA-DG
Public Made by Adomby adom
Sillumin Gate Drive ICs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 8d ago |
| viewers | 8d ago |
| package.json | 8d ago |
| page.json | 8d ago |
| README.md | 8d ago |
| slm27211ca-dg-etched.glb | 8d ago |
| slm27211ca-dg-etched.step | 8d ago |
| slm27211ca-dg-hero.glb | 8d ago |
| slm27211ca-dg-hero.overlay.json | 8d ago |
| slm27211ca-dg.glb | 8d ago |
| slm27211ca-dg.kicad_mod | 8d ago |
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| slm27211ca-dg.lbr | 8d ago |
| slm27211ca-dg.step | 8d ago |
| verification.json | 8d ago |
SLM27211CA-DG
Sillumin · Gate Drive ICs · SOP-8
SLM27211CA-DG from Sillumin, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply to the lower-gate driver; decouple to VSS (GND) with a capacitor of 0.22 µF to 4.7 µF, and the operating supply range is 8 V to 17 V. |
| 2 | HB | power_in | High-side bootstrap supply; the bootstrap diode is on-chip but an external bootstrap capacitor (typically 0.022 µF to 0.1 µF) is required between HB and HS, and VHB is rated up to 120 V. |
| 3 | HO | output | High-side gate driver output; connect to the gate of the high-side power MOSFET. |
| 4 | HS | power_in | High-side source connection; connect to the source of the high-side power MOSFET and to the negative side of the bootstrap capacitor, with voltage on HS rated up to 120 V DC. |
| 5 | HI | input | High-side input; assumed driven from a source impedance below 100 Ω, otherwise add a 1 nF to 10 nF capacitor between HI and VSS to avoid logic malfunction from noise. |
| 6 | LI | input | Low-side input; assumed driven from a source impedance below 100 Ω, otherwise add a 1 nF to 10 nF capacitor between LI and VSS to avoid logic malfunction from noise. |
| 7 | VSS | power_in | Negative supply terminal for the device, generally grounded; all voltages are referenced to VSS. |
| 8 | LO | output | Low-side gate driver output; connect to the gate of the low-side power MOSFET. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Sillumin |
| Package | SOP-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range on VDD | VDD | 8 | 12 | 17 | V | 6 | |
| Voltage between HB and HS | VBS | 8 | 12 | 17 | V | 6 | |
| Voltage on HS | VHS | -1 | 105 | V | 6 | ||
| Voltage on HS (repetitive pulse) | VHS | 110 | V | Repetitive pulse < 100 ns; min printed as -(24 V, VDD) | 6 | ||
| Voltage on HB | VHB | 115 | V | Min printed as VHS + 8 or VDD, 1; max printed as VHS + 17 or 115 | 6 | ||
| Voltage slew rate on HS | 50 | V/ns | 6 | ||||
| Operating junction temperature | TJ | -40 | 125 | °C | 6 | ||
| Supply voltage range, VDD, VHB, VHS | VDD | -0.3 | 20 | V | 5 | ||
| Input voltages on LI and HI | VLI, VHI | -0.3 | 20 | V | 5 | ||
| Output voltage on LO, DC | VLO | -0.3 | V | DC; max printed as VDD + 0.3 | 5 | ||
| Output voltage on LO, repetitive pulse | VLO | -2 | V | Repetitive pulse < 100 ns; max printed as VDD + 0.3 | 5 | ||
| Voltage on HS, DC | VHS | -1 | 120 | V | DC | 5 | |
| Voltage on HS, repetitive pulse | VHS | 120 | V | Repetitive pulse < 100 ns; min printed as -(24 V, VDD) | 5 | ||
| Voltage on HB | VHB | -0.3 | 120 | V | 5 | ||
| Operating virtual junction temperature range | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | TSTG | -65 | 150 | °C | 5 | ||
| ESD HBM | VESD | -2000 | 2000 | V | HBM | 5 | |
| ESD CDM | VESD | -1000 | 1000 | V | CDM | 5 | |
| VDD quiescent current | IDD | 0.08 | 0.115 | 0.15 | mA | V(LI) = V(HI) = 0 V | 7 |
| VDD operation current | IDDO | 0.7 | 1 | 1.5 | mA | f = 500 kHz, CLOAD = 0 | 7 |
| Boot voltage quiescent current | IHB | 0.07 | 0.095 | 0.12 | mA | V(LI) = V(HI) = 0 V | 7 |
| Boot voltage operating current | IHBO | 0.7 | 0.96 | 1.2 | mA | f = 500 kHz, CLOAD = 0 | 7 |
| HB to VSS quiescent current | IHBS | 0.02 | 1 | µA | V(HS) = V(HB) = 115 V | 7 | |
| HB to VSS operating current | IHBSO | 0.15 | 0.5 | mA | f = 500 kHz, CLOAD = 0 | 7 | |
| Input voltage threshold (HI) | VHIT | 1.9 | 2.3 | 2.6 | V | 7 | |
| Input voltage threshold (LI) | VLIT | 1.3 | 1.6 | 1.9 | V | 7 | |
| VDD turn on threshold | VDDR | 6.4 | 7 | 7.7 | V | 7 | |
| VHB turn on threshold | VHBR | 5.7 | 6.7 | 7.7 | V | 7 | |
| Low-current forward voltage | VF | 0.4 | 0.7 | V | IVDD-HB = 100 µA | 7 | |
| High-current forward voltage | VFI | 0.82 | 0.95 | V | IVDD-HB = 100 mA | 7 | |
| Dynamic resistance, ΔVF/ΔI | RD | 0.8 | 1 | 1.2 | Ω | IVDD-HB = 100 mA and 80 mA | 7 |
| LO low-level output voltage | VLOL | 0.04 | 0.08 | 0.18 | V | ILO = 100 mA | 7 |
| LO high level output voltage | VLOH | 0.12 | 0.18 | 0.25 | V | ILO = -100 mA, VLOH = VDD, VLO | 7 |
| HO low-level output voltage | VHOL | 0.04 | 0.08 | 0.18 | V | IHO = 100 mA | 7 |
| HO high-level output voltage | VHOH | 0.12 | 0.18 | 0.25 | V | IHO = -100 mA, VHOH = VHB, VHO | 7 |
| VLI falling to VLO falling | TDLFF | 18 | 22 | 30 | ns | CLOAD = 0 | 8 |
| VHI falling to VHO falling | TDHFF | 18 | 22 | 30 | ns | CLOAD = 0 | 8 |
| VLI rising to VLO rising | TDLRR | 17 | 21 | 29 | ns | CLOAD = 0 | 8 |
| VHI rising to VHO rising | TDHRR | 17 | 21 | 29 | ns | CLOAD = 0 | 8 |
| From HO OFF to LO ON | TMON | 2 | 7 | ns | 8 | ||
| From LO OFF to HO ON | TMOFF | 2 | 7 | ns | 8 | ||
| LO, HO rise time | tR | 0.35 | 0.5 | µs | CLOAD = 0.1 µF, (3 V to 9 V) | 8 | |
| LO, HO fall time | tF | 0.16 | 0.3 | µs | CLOAD = 0.1 µF, (9 V to 3 V) | 8 | |
| Input voltage hysteresis | VIHYS | 700 | mV | 7 | |||
| Input pulldown resistance | RIN | 55 | kΩ | 7 | |||
| VDD UVLO hysteresis | VDDHYS | 0.5 | V | 7 | |||
| VHB UVLO hysteresis | VHBHYS | 1.1 | V | 7 | |||
| Peak pull-up current (LO) | ISRC_L | 3 | A | VLO = 0 V | 7 | ||
| Peak pull-down current (LO) | ISNK_L | 4.5 | A | VLO = 12 V | 7 | ||
| Peak pull-up current (HO) | ISRC_H | 3 | A | VHO = 0 V | 7 | ||
| Peak pull-down current (HO) | ISNK_H | 4.5 | A | VHO = 12 V | 7 | ||
| LO rise time | tR | 7 | ns | CLOAD = 1000 pF, from 10% to 90% | 8 | ||
| HO rise time | tR | 7 | ns | 8 | |||
| LO fall time | tF | 5 | ns | CLOAD = 1000 pF, from 90% to 10% | 8 | ||
| HO fall time | tF | 5 | ns | 8 | |||
| Minimum input pulse width that changes the output | 50 | ns | 8 | ||||
| Bootstrap diode turn off time | 20 | ns | IF = 20 mA, IREV = 0.5 A | 8 | |||
| Thermal resistance junction-to-ambient, SOP8 | θJA | 111.8 | ℃/W | 5 |
CAD (KiCad official)
- Symbol:
SLM27211CA-DG - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
slm27211ca-dg-etched.step/slm27211ca-dg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);slm27211ca-dg.step/slm27211ca-dg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Sillumin datasheet (17 pp, sha256
4deec1e5e09db5d9, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).