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docs sl9451: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json sl9451: specified limits as data (metadata.characteristics, 17 rows from the datasheet) · Ray
README.md sl9451: specified limits as data (metadata.characteristics, 17 rows from the datasheet) · Ray
sl9451-etched.fit.json sl9451: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sl9451-etched.glb sl9451: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sl9451-etched.step sl9451: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sl9451.glb Publish 0.1.0 · Ray
sl9451.kicad_mod Publish 0.1.0 · Ray
sl9451.kicad_sym Publish 0.1.0 · Ray
sl9451.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sl9451.step Publish 0.1.0 · Ray

SL9451

Slkor SLKORMICRO Elec · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-6L

SL9451 from Slkor SLKORMICRO Elec, in a SOT-23-6L. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BST passive Bootstrap pin. Positive supply for the internal floating high-side MOSFET driver. Connect a bypass capacitor (typ. 100nF) between this pin and SW; internally charged to about 5V via an internal bootstrap regulator.
2 GND power_in Ground pin. Route as close as possible to the output capacitor, avoiding high-current switching paths.
3 FB input Feedback input to the error amplifier. An external resistor divider from VOUT to GND compared against the internal 0.794V (typ) reference sets the regulated output voltage. Also interacts with the internal RC compensation network.
4 EN input Enable input. Drive above ~1.6V (typ 2.0V) to enable the chip; pull below the threshold to shut down. 0.6V hysteresis; internally clamped to 7.5V. Floating pulls low internally (device disabled).
5 VIN power_in Power input, 4.2V to 40V (abs max 43V). Supplies all internal control circuitry and the high-side power switch. Requires a local decoupling capacitor (typ 4.7uF/50V) to GND to reduce switching spikes.
6 SW output Switch node - high-side power MOSFET output (500mΩ Rdson typ, 1A current limit). Connect to the inductor and a low-Vf Schottky freewheel diode to GND placed close to the pin to reduce switching spikes.

Key specifications

Parameter Value
Manufacturer Slkor SLKORMICRO Elec
Package SOT-23-6L
Category PMIC
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Feedback voltage Vfb 0.778 0.794 0.81 V 4
Oscillator frequency Fosc 1.4 1.8 2.2 MHz 4
Minimum operating voltage Vin min 4.2 V 4
Minimum switch on-time Ton min 100 ns 4
Input voltage VIN VIN -0.3 43 V 3
Switch voltage VSW (max = VIN(MAX)+0.3V) VSW -0.3 V VSW max = VIN(MAX)+0.3V as printed 3
BST to SW voltage VBST-VSW -0.3 6 V 3
Other pins voltage -0.3 5 V 3
Continuous power dissipation PD 0.57 W TA=+25°C 3
Junction temperature TJ 150 °C 3
Lead temperature 260 °C 3
Storage temperature TSTG -65 150 °C 3
Supply voltage VIN VIN 4.2 40 V 3
SW terminal voltage VOUT 40 V Up to 40V as printed 3
Operating junction temperature TJ -40 125 °C 3
Thermal resistance junction-to-ambient, SOT23-6L θJA 220 °C/W SOT23-6L; table has no min/typ/max header 3
Thermal resistance junction-to-case, SOT23-6L θJC 110 °C/W SOT23-6L; table has no min/typ/max header 3

CAD (KiCad official)

  • Symbol: SL9451
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6L (KiCad packages3D, STEP)
  • 3D model files: sl9451-etched.step / sl9451-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sl9451.step / sl9451.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sl9451.step 97 KB You want the bare part, or you mark your own boards.
sl9451-etched.step 1.3 MB You want the part with SL9451 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 332 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Slkor SLKORMICRO Elec datasheet (9 pp, sha256 e647ca8661d4bc1f, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF