component
SL8563T-G
Public Made by Adomby adom
Slkor SLKORMICRO Elec Real Time Clocks, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SL8563T-G
Slkor SLKORMICRO Elec · Real Time Clocks · SOP-8
SL8563T-G from Slkor SLKORMICRO Elec, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OSCI | input | Oscillator input for the external 32.768kHz crystal; the OSCI absolute input range is -0.5V to VDD+0.5V. |
| 2 | OSCO | output | Oscillator output for the external 32.768kHz crystal; see note 3 on page 16 for its use. |
| 3 | INT | output | Interrupt output for the alarm and periodic timer flags, with pulse or level behavior selected by TI/TP (register 01H); the absolute output voltage limit is -0.5V to +6.5V. |
| 4 | VSS | power_in | Ground reference for the device. |
| 5 | SDA | bidirectional | I2C serial data line; VIL is 0 to 0.3VDD and VIH is 0.7VDD to VDD, with absolute limits of -0.5V to +6.5V. |
| 6 | SCL | input | I2C serial clock input, up to 400kHz; absolute input limits are -0.5V to +6.5V. |
| 7 | CLKOUT | output | Programmable clock output selectable as 32.768kHz, 1024Hz, 32Hz or 1Hz via register 0DH and enabled by the FE bit; absolute output limits are -0.5V to +6.5V. |
| 8 | VDD | power_in | Supply voltage: 1.0V to 5.5V for I2C communication and 1.8V to 5.5V at 400kHz, with absolute limits of -0.5V to +6.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Slkor SLKORMICRO Elec |
| Package | SOP-8 |
| Category | Clock/Timing |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | -0.5 | 6.5 | V | 3 | ||
| Power supply current | IDD | -50 | 50 | mA | 3 | ||
| SCL and SDA input voltage | VI | -0.5 | 6.5 | V | 3 | ||
| OSCI input voltage | -0.5 | V | 3 | ||||
| CLKOUT and output voltage | VO | -0.5 | 6.5 | V | 3 | ||
| Digital input current | II | -10 | 10 | mA | 3 | ||
| Digital output current | IO | -10 | 10 | mA | 3 | ||
| Power dissipation | PD | 300 | mW | 3 | |||
| Operating ambient temperature | TA | -40 | 85 | ℃ | 3 | ||
| Storage temperature | TS | -65 | 150 | ℃ | 3 | ||
| Supply voltage, I2C bus operation | VDD | 1 | 5.5 | V | I2C bus operation, TA ℃ | 3 | |
| Supply voltage, I2C at 400kHz | VDD | 1.8 | 5.5 | V | I2C at f=400kHz | 3 | |
| Supply voltage, clock/calendar data retention | VDD | 5.5 | V | TA ℃; minimum printed as Vlow | 3 | ||
| Supply current, CLKOUT on | IDD1 | 800 | uA | CLKOUT on (FE=1), fSCL=400kHz | 3 | ||
| Supply current, CLKOUT on | IDD1 | 200 | uA | CLKOUT on (FE=1), fSCL=100kHz | 3 | ||
| Supply current, CLKOUT off | IDD2 | 4 | 6 | uA | CLKOUT off (FE=0), fSCL=0Hz, TA=25℃, VDD=5.0V; SCL and SDA tied to VDD (note 2) | 3 | |
| Supply current, CLKOUT off | IDD2 | 2 | 4 | uA | CLKOUT off (FE=0), fSCL=0Hz, TA=25℃, VDD=3.0V; SCL and SDA tied to VDD (note 2) | 3 | |
| Supply current, CLKOUT off | IDD2 | 500 | 800 | nA | CLKOUT off (FE=0), fSCL=0Hz, TA=25℃, VDD=2.0V; SCL and SDA tied to VDD (note 2) | 3 | |
| Supply current, CLKOUT off | IDD2 | 500 | 750 | nA | CLKOUT off (FE=0), fSCL=0Hz, TA=-40~+85℃, VDD=5.0V; SCL and SDA tied to VDD (note 2) | 3 | |
| Supply current, CLKOUT 32.768kHz | IDD3 | 9 | 13 | uA | CLKOUT=32.768kHz, fSCL=0Hz, TA=25℃, VDD=5.0V; SCL and SDA tied to VDD (note 2) | 3 | |
| Supply current, CLKOUT 32.768kHz | IDD3 | 7 | 10 | uA | CLKOUT=32.768kHz, fSCL=0Hz, TA=25℃, VDD=3.0V; SCL and SDA tied to VDD (note 2) | 3 | |
| Supply current, CLKOUT 32.768kHz | IDD3 | 3 | 5 | uA | CLKOUT=32.768kHz, fSCL=0Hz, TA=25℃, VDD=2.0V; SCL and SDA tied to VDD (note 2) | 3 | |
| Supply current, CLKOUT 32.768kHz | IDD3 | 7 | 10 | uA | CLKOUT=32.768kHz, fSCL=0Hz, TA=-40~+85℃, VDD=3.0V; SCL and SDA tied to VDD (note 2) | 4 | |
| Supply current, CLKOUT 32.768kHz | IDD3 | 3 | 5 | uA | CLKOUT=32.768kHz, fSCL=0Hz, TA=-40~+85℃, VDD=2.0V; SCL and SDA tied to VDD (note 2) | 4 | |
| Input leakage current | ILI | -1 | 0 | 1 | μA | VI=VDD to VSS | 4 |
| Input capacitance | CI | 7 | pF | 4 | |||
| SDA low-level output current | IOLS | -3 | mA | VOL=0.4V, VDD=5.0V | 4 | ||
| SDA low-level output current | IOLI | -1 | mA | VOL=0.4V, VDD=5.0V | 4 | ||
| CLKOUT low-level output current | IOLC | -1 | mA | VOL=0.4V, VDD=5.0V | 4 | ||
| CLKOUT high-level output current | IOHC | 1 | mA | VOL=4.6V (as printed), VDD=5.0V | 4 | ||
| Output leakage current | ILO | -1 | 0 | 1 | μA | VO=VDD to VSS | 4 |
| Data retention voltage | VLOW | 0.9 | 1 | V | TA ℃ | 4 | |
| Internal oscillator capacitance | CINT | 15 | 25 | 35 | pF | 4 | |
| Oscillator series resistance | RS | 40 | kΩ | f=32.768kHz | 4 | ||
| Trimmer capacitance | CT | 5 | 25 | pF | 4 | ||
| I2C SCL clock frequency | fSCL | 400 | kHz | 4 | |||
| START hold time | tHDSTA | 0.6 | μs | 4 | |||
| START setup time | tSUSTA | 0.6 | μs | 4 | |||
| SCL low period | tLOW | 1.3 | μs | 4 | |||
| SCL high period | tHIGH | 0.6 | μs | 4 | |||
| SCL and SDA rise time | tr | 0.3 | μs | 4 | |||
| SCL and SDA fall time | tf | 0.3 | μs | 4 | |||
| I2C bus capacitive load | Cb | 400 | pF | 4 | |||
| Data setup time | tSUDAT | 100 | ns | 4 | |||
| Data hold time | tHDDAT | 0 | ns | 4 | |||
| STOP setup time | tSUSTO | 0.6 | μs | 5 | |||
| Input spike suppression width | tSW | 50 | ns | 5 | |||
| Oscillator load capacitance | CL | 10 | pF | 4 | |||
| CLKOUT duty cycle | δ CLKOUT | 50 | % | fCLKOUT = 32.768kHz (note 1) | 4 |
CAD (KiCad official)
- Symbol:
SL8563T-G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
sl8563t-g-etched.step/sl8563t-g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sl8563t-g.step/sl8563t-g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Slkor SLKORMICRO Elec datasheet (17 pp, sha256
d07cd38dc23ea71b, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SL8563T-G
**Slkor SLKORMICRO Elec** · Real Time Clocks · SOP-8
SL8563T-G from Slkor SLKORMICRO Elec, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OSCI | input | Oscillator input for the external 32.768kHz crystal; the OSCI absolute input range is -0.5V to VDD+0.5V. |
| 2 | OSCO | output | Oscillator output for the external 32.768kHz crystal; see note 3 on page 16 for its use. |
| 3 | INT | output | Interrupt output for the alarm and periodic timer flags, with pulse or level behavior selected by TI/TP (register 01H); the absolute output voltage limit is -0.5V to +6.5V. |
| 4 | VSS | power_in | Ground reference for the device. |
| 5 | SDA | bidirectional | I2C serial data line; VIL is 0 to 0.3VDD and VIH is 0.7VDD to VDD, with absolute limits of -0.5V to +6.5V. |
| 6 | SCL | input | I2C serial clock input, up to 400kHz; absolute input limits are -0.5V to +6.5V. |
| 7 | CLKOUT | output | Programmable clock output selectable as 32.768kHz, 1024Hz, 32Hz or 1Hz via register 0DH and enabled by the FE bit; absolute output limits are -0.5V to +6.5V. |
| 8 | VDD | power_in | Supply voltage: 1.0V to 5.5V for I2C communication and 1.8V to 5.5V at 400kHz, with absolute limits of -0.5V to +6.5V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Slkor SLKORMICRO Elec |
| Package | SOP-8 |
| Category | Clock/Timing |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | -0.5 | | 6.5 | V | | 3 |
| Power supply current | IDD | -50 | | 50 | mA | | 3 |
| SCL and SDA input voltage | VI | -0.5 | | 6.5 | V | | 3 |
| OSCI input voltage | | -0.5 | | | V | | 3 |
| CLKOUT and output voltage | VO | -0.5 | | 6.5 | V | | 3 |
| Digital input current | II | -10 | | 10 | mA | | 3 |
| Digital output current | IO | -10 | | 10 | mA | | 3 |
| Power dissipation | PD | | | 300 | mW | | 3 |
| Operating ambient temperature | TA | -40 | | 85 | ℃ | | 3 |
| Storage temperature | TS | -65 | | 150 | ℃ | | 3 |
| Supply voltage, I2C bus operation | VDD | 1 | | 5.5 | V | I2C bus operation, TA ℃ | 3 |
| Supply voltage, I2C at 400kHz | VDD | 1.8 | | 5.5 | V | I2C at f=400kHz | 3 |
| Supply voltage, clock/calendar data retention | VDD | | | 5.5 | V | TA ℃; minimum printed as Vlow | 3 |
| Supply current, CLKOUT on | IDD1 | | | 800 | uA | CLKOUT on (FE=1), fSCL=400kHz | 3 |
| Supply current, CLKOUT on | IDD1 | | | 200 | uA | CLKOUT on (FE=1), fSCL=100kHz | 3 |
| Supply current, CLKOUT off | IDD2 | | 4 | 6 | uA | CLKOUT off (FE=0), fSCL=0Hz, TA=25℃, VDD=5.0V; SCL and SDA tied to VDD (note 2) | 3 |
| Supply current, CLKOUT off | IDD2 | | 2 | 4 | uA | CLKOUT off (FE=0), fSCL=0Hz, TA=25℃, VDD=3.0V; SCL and SDA tied to VDD (note 2) | 3 |
| Supply current, CLKOUT off | IDD2 | | 500 | 800 | nA | CLKOUT off (FE=0), fSCL=0Hz, TA=25℃, VDD=2.0V; SCL and SDA tied to VDD (note 2) | 3 |
| Supply current, CLKOUT off | IDD2 | | 500 | 750 | nA | CLKOUT off (FE=0), fSCL=0Hz, TA=-40~+85℃, VDD=5.0V; SCL and SDA tied to VDD (note 2) | 3 |
| Supply current, CLKOUT 32.768kHz | IDD3 | | 9 | 13 | uA | CLKOUT=32.768kHz, fSCL=0Hz, TA=25℃, VDD=5.0V; SCL and SDA tied to VDD (note 2) | 3 |
| Supply current, CLKOUT 32.768kHz | IDD3 | | 7 | 10 | uA | CLKOUT=32.768kHz, fSCL=0Hz, TA=25℃, VDD=3.0V; SCL and SDA tied to VDD (note 2) | 3 |
| Supply current, CLKOUT 32.768kHz | IDD3 | | 3 | 5 | uA | CLKOUT=32.768kHz, fSCL=0Hz, TA=25℃, VDD=2.0V; SCL and SDA tied to VDD (note 2) | 3 |
| Supply current, CLKOUT 32.768kHz | IDD3 | | 7 | 10 | uA | CLKOUT=32.768kHz, fSCL=0Hz, TA=-40~+85℃, VDD=3.0V; SCL and SDA tied to VDD (note 2) | 4 |
| Supply current, CLKOUT 32.768kHz | IDD3 | | 3 | 5 | uA | CLKOUT=32.768kHz, fSCL=0Hz, TA=-40~+85℃, VDD=2.0V; SCL and SDA tied to VDD (note 2) | 4 |
| Input leakage current | ILI | -1 | 0 | 1 | μA | VI=VDD to VSS | 4 |
| Input capacitance | CI | | | 7 | pF | | 4 |
| SDA low-level output current | IOLS | -3 | | | mA | VOL=0.4V, VDD=5.0V | 4 |
| SDA low-level output current | IOLI | -1 | | | mA | VOL=0.4V, VDD=5.0V | 4 |
| CLKOUT low-level output current | IOLC | -1 | | | mA | VOL=0.4V, VDD=5.0V | 4 |
| CLKOUT high-level output current | IOHC | 1 | | | mA | VOL=4.6V (as printed), VDD=5.0V | 4 |
| Output leakage current | ILO | -1 | 0 | 1 | μA | VO=VDD to VSS | 4 |
| Data retention voltage | VLOW | | 0.9 | 1 | V | TA ℃ | 4 |
| Internal oscillator capacitance | CINT | 15 | 25 | 35 | pF | | 4 |
| Oscillator series resistance | RS | | | 40 | kΩ | f=32.768kHz | 4 |
| Trimmer capacitance | CT | 5 | | 25 | pF | | 4 |
| I2C SCL clock frequency | fSCL | | | 400 | kHz | | 4 |
| START hold time | tHDSTA | 0.6 | | | μs | | 4 |
| START setup time | tSUSTA | 0.6 | | | μs | | 4 |
| SCL low period | tLOW | 1.3 | | | μs | | 4 |
| SCL high period | tHIGH | 0.6 | | | μs | | 4 |
| SCL and SDA rise time | tr | | | 0.3 | μs | | 4 |
| SCL and SDA fall time | tf | | | 0.3 | μs | | 4 |
| I2C bus capacitive load | Cb | | | 400 | pF | | 4 |
| Data setup time | tSUDAT | 100 | | | ns | | 4 |
| Data hold time | tHDDAT | 0 | | | ns | | 4 |
| STOP setup time | tSUSTO | 0.6 | | | μs | | 5 |
| Input spike suppression width | tSW | | | 50 | ns | | 5 |
| Oscillator load capacitance | CL | | 10 | | pF | | 4 |
| CLKOUT duty cycle | δ CLKOUT | | 50 | | % | fCLKOUT = 32.768kHz (note 1) | 4 |
## CAD (KiCad official)
- Symbol: `SL8563T-G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `sl8563t-g-etched.step` / `sl8563t-g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sl8563t-g.step` / `sl8563t-g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Slkor SLKORMICRO Elec datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603127289726967808) (17 pp, sha256 `d07cd38dc23ea71b`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sl8563t-g-datasheet.pdf)