component

SL65HVD233DR

Public Made by Adom

by adom

Slkor SLKORMICRO Elec CAN Transceivers, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfacesl65hvd233drfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
sl65hvd233dr / README.md
History Download
Ray Publish 0.1.0 2d3f015 3h ago

SL65HVD233DR

Slkor SLKORMICRO Elec · CAN Transceivers · SOP-8

SL65HVD233DR from Slkor SLKORMICRO Elec, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D input CAN transmit data input (LOW for dominant and HIGH for recessive bus states), also called TXD, acting as the driver input.
2 GND power_in Ground reference for the transceiver; the datasheet states that the reference point for all voltages is ground.
3 VCC power_in Transceiver 3.3V supply voltage, specified as VCC = 3.3V ±10% for normal operation with an absolute maximum of -0.3 V to +6 V.
4 R output CAN receive data output (LOW for dominant and HIGH for recessive bus states), also called RXD, driven by the receiver.
5 LBK input Loopback mode input; a high level enables diagnostic loopback that disables the driver and routes D internally to R, and the pin is pulled low internally so it may be left open or tied to GND when unused.
6 CANL bidirectional Low-level CAN bus line, with bus terminal voltage rated from -36 V to +36 V.
7 CANH bidirectional High-level CAN bus line, with bus terminal voltage rated from -36 V to +36 V.
8 RS input Mode select: a strong pull-down to GND selects high-speed mode, a logic high above 0.75VCC selects standby (low-power) mode, and a 10 kΩ to 100 kΩ resistor to GND selects slope-control mode.

Key specifications

Parameter Value
Manufacturer Slkor SLKORMICRO Elec
Package SOP-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.3 6 V 3
DC voltage on D/R pins D, R -0.5 V Printed as -0.5~VCC+0.5; upper limit is VCC-relative, not numeric 3
Voltage range at any bus terminal CANL, CANH -36 36 V 3
Transient voltage on pins CANH, CANL Vtr -40 40 V test with 100Ω, see Fig 10 3
Receiver output current IO -11 11 mA 3
Storage temperature Tstg -40 150 ℃ 3
Virtual junction temperature Tj -40 125 ℃ 3
Supply voltage Vcc 3 3.6 V 1
Output voltage (Dominant), CANH VO(D) 2.45 V VI=0V, RS=0V, RL=60Ω (Fig1, Fig 2); printed max is VCC 4
Output voltage (Dominant), CANL VO(D) 0.5 1.25 V VI=0V, RS=0V, RL=60Ω (Fig1, Fig 2) 4
Differential output voltage (Dominant) VOD(D) 1.5 2 3 V VI=0V, RS=0V, RL=60Ω (Fig 1) 4
Differential output voltage (Dominant) VOD(D) 1.2 2 3 V VI=0V, RL=60Ω, RS=0V (Fig 3) 4
Differential output voltage (Recessive) VOD(R) -0.12 0.012 V VI=3V, RS=0V 4
Differential output voltage (Recessive) VOD(R) -0.5 0.05 V VI=3V, RS=0V, No load 4
High-level input current IIH -30 30 μA VI=2V 4
Low-level input current IIL -30 30 μA VI=0.8V 4
Short-circuit output current IOS -250 mA CANH=-7V 4
Short-circuit output current IOS 1 mA CANH=12V 4
Short-circuit output current IOS -1 mA CANL=-7V 4
Short-circuit output current IOS 250 mA CANL=12V 4
Power consumption in standby mode ICC 650 950 μA RS=VCC, VI=VCC 7
Dominant power consumption ICC 50 70 mA VI=0V, RS=0V, LOAD=60Ω 7
Recessive power consumption ICC 6 mA VI=VCC, RS=0V, No load 7
Propagation delay time (low-to-high-level) tPLH 35 85 ns R=0, Short circuit (Fig 4) 4
Propagation delay time (low-to-high-level) tPLH 70 125 ns R=10kΩ 4
Propagation delay time (low-to-high-level) tPLH 500 870 ns R=100kΩ 4
Propagation delay time (high-to-low-level) tPHL 70 120 ns R=0, Short circuit (Fig 4) 5
Propagation delay time (high-to-low-level) tPHL 130 180 ns R=10kΩ 5
Propagation delay time (high-to-low-level) tPHL 870 1200 ns R=100kΩ 5
Pulse skew (/tPLH - tPHL/) tsk(p) 35 ns R=0, Short circuit (Fig 4) 5
Pulse skew (/tPLH - tPHL/) tsk(p) 60 ns R=10kΩ 5
Pulse skew (/tPLH - tPHL/) tsk(p) 370 ns R=100kΩ 5
Differential output signal rise time tr 20 80 ns R=0, Short circuit (Fig 4) 5
Differential output signal rise time tr 30 160 ns R=10kΩ 5
Differential output signal rise time tr 300 1400 ns R=100kΩ 5
Differential output signal fall time tf 20 80 ns R=0, Short circuit (Fig 4) 5
Differential output signal fall time tf 30 160 ns R=10kΩ 5
Differential output signal fall time tf 300 1400 ns R=100kΩ 5
Positive-going input threshold voltage VIT+ 750 900 mV Table 1 5
Negative-going input threshold voltage VIT- 500 650 mV Table 1 5
Hysteresis voltage Vhys 100 mV VIT+ - VIT- 5
High-level output voltage VOH 2.4 V -6V<VID<500mV, IO=-8mA (Fig5) 5
Low-level output voltage VOL 0.4 V 900mV<VID<6V, IO=8mA (Fig5) 5
Bus input current Ii 100 600 μA VIH=12V, VCC=0V 5
Bus input current Ii 100 500 μA VIH=12V, VCC=3.3V 5
Bus input current Ii -450 -20 μA VIH=-7V, VCC=0V 5
Bus input current Ii -610 -30 μA VIH=-7V, VCC=3.3V 5
Bus input resistance Ri 20 35 50 kΩ Corresponding standards of ISO 11898-2 5
Propagation delay time (low-to-high-level) tPLH 35 60 ns Fig 6 6
Propagation delay time (high-to-low-level) tPHL 35 60 ns Fig 6 6
Pulse skew /tPHL - tPLH/ tsk 10 ns 6
Differential input resistance Rdiff 40 100 kΩ Corresponding standards of ISO 11898-2 6
Total loop delay, driver input to receiver output, recessive to dominant t(LOOP1) 70 135 ns R=0, Short circuit (Fig 8) 6
Total loop delay, driver input to receiver output, recessive to dominant t(LOOP1) 105 190 ns R=10 kΩ 6
Total loop delay, driver input to receiver output, recessive to dominant t(LOOP1) 535 1000 ns R=100 kΩ 6
Total loop delay, driver input to receiver output, dominant to recessive t(LOOP2) 70 165 ns R=0, Short circuit (Fig 8) 6
Total loop delay, driver input to receiver output, dominant to recessive t(LOOP2) 105 190 ns R=10 kΩ 6
Total loop delay, driver input to receiver output, dominant to recessive t(LOOP2) 535 1000 ns R=100 kΩ 6
Lookback delay, driver input to receiver output t(LBK) 7.5 12 ns Fig 9 6
Thermal shutdown temperature Tj(sd) 155 165 180 ℃ 7
Wake-up time from standby mode TWAKE 0.55 1.5 μs RS adds square wave (Fig7) 7

CAD (KiCad official)

  • Symbol: SL65HVD233DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: sl65hvd233dr-etched.step / sl65hvd233dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sl65hvd233dr.step / sl65hvd233dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Slkor SLKORMICRO Elec datasheet (16 pp, sha256 574ee6251c10cea8, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF