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SL65HVD232DR

Slkor SLKORMICRO Elec · CAN Transceivers · SOP-8

SL65HVD232DR from Slkor SLKORMICRO Elec, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D input CAN transmit data input (TXD, driver input): LOW drives the bus dominant and HIGH releases it to recessive.
2 GND power_in Ground connection; the datasheet states all voltages are referenced to ground.
3 VCC power_in Transceiver 3.3V supply voltage, specified at 3 V to 3.6 V in the absolute maximum ratings table.
4 R output CAN receive data output (RXD): LOW for a dominant and HIGH for a recessive bus state.
5 NC unconnected Not connected.
6 CANL bidirectional Low-level CAN bus line; the CANH/CANL bus pins are rated for input or output voltage of -16 V to +16 V.
7 CANH bidirectional High-level CAN bus line; the CANH/CANL bus pins are rated for input or output voltage of -16 V to +16 V.
8 NC unconnected Not connected.

Key specifications

Parameter Value
Manufacturer Slkor SLKORMICRO Elec
Package SOP-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Maximum transmission rate 1/tbit 1 Mbaud Non return to zero code 1
Supply voltage Vcc 3 3.6 V 1
CANH/CANL input or output voltage Vcan -16 16 V 1
Bus differential voltage Vdiff 1.5 3 V 1
Virtual junction temperature Tamb -40 125 ℃ 1
Supply voltage VCC -0.3 6 V 3
DC voltage on D/R pins D, R -0.5 V 3
Voltage range at any bus terminal (CANH, CANL) CANL, CANH -18 18 V 3
Transient voltage on pins 6, 7 Vtr -25 25 V 3
Receiver output current IO -11 11 mA 3
Storage temperature Tstg -40 150 ℃ 3
Virtual junction temperature Tj -40 125 ℃ 3
Continuous total power dissipation 400 mW SOP8 3
Output voltage (Dominant) CANH VO(D) 2.45 V VI=0V, RL=60Ω, Fig 1, Fig 2 4
Output voltage (Dominant) CANL VO(D) 0.5 1.25 V VI=0V, RL=60Ω, Fig 1, Fig 2 4
Differential output voltage (Dominant) VOD(D) 1.5 2 3 V VI=0V, RL=60Ω, Fig 1 4
Differential output voltage (Dominant) VOD(D) 1.2 2 3 V VI=0V, RL=60Ω, RS=0V, Fig 3 4
Output voltage (Recessive) CANH VO(R) 2.3 V VI=3V, RL=60Ω, Fig 1 4
Differential output voltage (Recessive) VOD(R) -0.12 0.012 V VI=3V 4
Differential output voltage (Recessive) VOD(R) -0.5 0.05 V VI=3V, No load 4
High level input current IIH -30 μA VI=2V 4
Low level input current IIL -30 μA VI=0.8V 4
Short circuit output current IOS -250 mA CANH=-2V 4
Short circuit output current IOS 1 mA CANH=7V 4
Short circuit output current IOS -1 mA CANL=-2V 4
Short circuit output current IOS 250 mA CANL=7V 4
Supply current ICC 10 17 mA VI=0V (Dominant), No load 4
Propagation delay time (low-to-high level) tPLH 35 85 ns R=0, short circuit, Fig 4 4
Propagation delay time (low-to-high level) tPLH 70 125 ns R=10kΩ 4
Propagation delay time (high-to-low level) tPHL 70 120 ns R=0, short circuit, Fig 4 5
Propagation delay time (high-to-low level) tPHL 130 180 ns R=10kΩ 5
Pulse skew (/tPLH - tPHL/) tsk(p) 35 ns R=0, short circuit, Fig 4 5
Pulse skew (/tPLH - tPHL/) tsk(p) 60 ns R=10kΩ 5
Differential output signal rise time tr 25 50 100 ns R=0, short circuit, Fig 4 5
Differential output signal rise time tr 80 120 160 ns R=10kΩ 5
Differential output signal fall time tf 40 55 80 ns R=0, short circuit, Fig 4 5
Differential output signal fall time tf 80 125 150 ns R=10kΩ 5
Positive-going input threshold voltage VIT+ 750 900 mV Table 1 5
Negative-going input threshold voltage VIT- 500 650 mV Table 1 5
Hysteresis voltage Vhys 100 mV VIT+ - VIT- 5
High-level output voltage VOH 2.4 V -6V<VID<500mV, IO=-8mA, Fig 5 5
Low-level output voltage VOL 0.4 V 900mV<VID<6V, IO=8mA, Fig 5 5
Bus input current Ii 100 350 μA VIH=7V, VCC=0V 5
Bus input current Ii 100 250 μA VIH=7V, VCC=3.3V 5
Bus input current Ii -100 -20 μA VIH=-2V, VCC=0V 5
Bus input current Ii -200 -30 μA VIH=-2V, VCC=3.3V 5
Input resistance Ri 20 35 50 kΩ ISO 11898-2 standard 5
Propagation delay time (low-to-high level) tPLH 35 50 ns Fig 6 6
Propagation delay time (high-to-low level) tPHL 35 50 ns Fig 6 6
Pulse skew tsk 10 ns /tPHL - tPLH/ 6
Differential input resistance Rdiff 40 100 kΩ ISO 11898-2 standard 6
Input capacitance Ci 40 pF ISO 11898-2 standard 6
Differential input capacitance Cdiff 20 pF ISO 11898-2 standard 6
Loop delay 1, driver input to receiver output, Recessive to Dominant t(LOOP1) 70 115 ns R=0, short circuit, Fig 7 6
Loop delay 2, driver input to receiver output, Dominant to Recessive t(LOOP2) 100 135 ns R=0, short circuit, Fig 7 6
Shutdown junction temperature Tj(sd) 155 165 180 ℃ 7
Dominant power consumption ICC 50 70 mA VI=0V, LOAD=60Ω 7
Recessive power consumption ICC 6 10 mA VI=VCC, No load 7

CAD (KiCad official)

  • Symbol: SL65HVD232DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: sl65hvd232dr-etched.step / sl65hvd232dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sl65hvd232dr.step / sl65hvd232dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Slkor SLKORMICRO Elec datasheet (14 pp, sha256 4763cfe043dad469, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF