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SL4813A
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Slkor SLKORMICRO Elec MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SL4813A
Slkor SLKORMICRO Elec · MOSFETs · SOP-8
SL4813A from Slkor SLKORMICRO Elec, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of P-channel MOSFET 1. |
| 2 | G1 | input | Gate of P-channel MOSFET 1, with a VGS rating of ±20 V. |
| 3 | S2 | passive | Source of P-channel MOSFET 2. |
| 4 | G2 | input | Gate of P-channel MOSFET 2, with a VGS rating of ±20 V. |
| 5 | D2 | passive | Drain of P-channel MOSFET 2, tied to pin 6, with a VDS rating of -30 V. |
| 6 | D2 | passive | Drain of P-channel MOSFET 2, tied to pin 5, with a VDS rating of -30 V. |
| 7 | D1 | passive | Drain of P-channel MOSFET 1, tied to pin 8, with a VDS rating of -30 V. |
| 8 | D1 | passive | Drain of P-channel MOSFET 1, tied to pin 7, with a VDS rating of -30 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Slkor SLKORMICRO Elec |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source Voltage | VDS | -30 | V | 1 | |||
| Gate-source Voltage | VGS | -20 | 20 | V | 1 | ||
| Drain Current | ID | -7.1 | A | 1 | |||
| Pulsed Drain Current | IDM | -20 | A | Note A: pulse width ≤300us, duty cycle ≤2% | 1 | ||
| Total Power Dissipation | PD | 2.5 | W | TA=25℃ | 1 | ||
| Total Power Dissipation | PD | 1.6 | W | TA=70℃ | 1 | ||
| Thermal Resistance Junction-to-Ambient | RθJA | 50 | ℃/W | Note B: mounted on a 1 in 2 pad of 2oz copper | 1 | ||
| Junction and Storage Temperature Range | TJ ,TSTG | -55 | 150 | ℃ | 1 | ||
| Drain-Source Breakdown Voltage | BVDSS | -30 | V | VGS=0V, ID=-250μA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | -1 | μA | VDS=-30V,VGS=0V | 2 | ||
| Gate-Body Leakage Current | IGSS | -100 | 100 | nA | VGS=±20V, VDS=0V | 2 | |
| Gate Threshold Voltage | VGS(th) | -1 | -1.5 | -2.5 | V | VDS= VGS, ID=-250μA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | 20 | 25 | mΩ | VGS=-10V, ID=-7A | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 30 | 40 | mΩ | VGS=-4.5V, ID=-5A | 2 | |
| Diode Forward Voltage | VSD | -1.2 | V | IS=-7A,VGS=0V | 2 | ||
| Input Capacitance | Ciss | 1488 | pF | VDS=-15V,VGS=0V,f=1MHZ | 2 | ||
| Output Capacitance | Coss | 178 | pF | VDS=-15V,VGS=0V,f=1MHZ | 2 | ||
| Reverse Transfer Capacitance | Crss | 164 | pF | VDS=-15V,VGS=0V,f=1MHZ | 2 | ||
| Total Gate Charge | Qg | 28.44 | nC | VGS=-10V,VDS=-15V,ID=-7.1A | 2 | ||
| Gate-Source Charge | Qgs | 5.25 | nC | VGS=-10V,VDS=-15V,ID=-7.1A | 2 | ||
| Gate-Drain Charge | Qgd | 5.17 | nC | VGS=-10V,VDS=-15V,ID=-7.1A | 2 | ||
| Reverse Recovery Charge | Qrr | 5.3 | IF=-5A, di/dt=100A/us | 2 | |||
| Reverse Recovery Time | trr | 14 | ns | IF=-5A, di/dt=100A/us | 2 | ||
| Turn-on Delay Time | tD(on) | 10 | ns | VGS=-10V, VDS=-15V, ID=-7.1A RGEN=2.5Ω | 2 | ||
| Turn-on Rise Time | tr | 44 | ns | VGS=-10V, VDS=-15V, ID=-7.1A RGEN=2.5Ω | 2 | ||
| Turn-off Delay Time | tD(off) | 54 | ns | VGS=-10V, VDS=-15V, ID=-7.1A RGEN=2.5Ω | 2 | ||
| Turn-off Fall Time | tf | 58 | ns | VGS=-10V, VDS=-15V, ID=-7.1A RGEN=2.5Ω | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | mounting surface of the drain pins. RθJC is guaranteed by design, while RθJA is determined by the board design. The maximum rating presented here is based on mounting on a 1 in 2 pad of 2oz copper. | 2 |
CAD (KiCad official)
- Symbol:
SL4813A - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
sl4813a-etched.step/sl4813a-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sl4813a.step/sl4813a.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Slkor SLKORMICRO Elec datasheet (5 pp, sha256
312361d6da68706c, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SL4813A
**Slkor SLKORMICRO Elec** · MOSFETs · SOP-8
SL4813A from Slkor SLKORMICRO Elec, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of P-channel MOSFET 1. |
| 2 | G1 | input | Gate of P-channel MOSFET 1, with a VGS rating of ±20 V. |
| 3 | S2 | passive | Source of P-channel MOSFET 2. |
| 4 | G2 | input | Gate of P-channel MOSFET 2, with a VGS rating of ±20 V. |
| 5 | D2 | passive | Drain of P-channel MOSFET 2, tied to pin 6, with a VDS rating of -30 V. |
| 6 | D2 | passive | Drain of P-channel MOSFET 2, tied to pin 5, with a VDS rating of -30 V. |
| 7 | D1 | passive | Drain of P-channel MOSFET 1, tied to pin 8, with a VDS rating of -30 V. |
| 8 | D1 | passive | Drain of P-channel MOSFET 1, tied to pin 7, with a VDS rating of -30 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Slkor SLKORMICRO Elec |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source Voltage | VDS | | | -30 | V | | 1 |
| Gate-source Voltage | VGS | -20 | | 20 | V | | 1 |
| Drain Current | ID | | | -7.1 | A | | 1 |
| Pulsed Drain Current | IDM | | | -20 | A | Note A: pulse width ≤300us, duty cycle ≤2% | 1 |
| Total Power Dissipation | PD | | | 2.5 | W | TA=25℃ | 1 |
| Total Power Dissipation | PD | | | 1.6 | W | TA=70℃ | 1 |
| Thermal Resistance Junction-to-Ambient | RθJA | | | 50 | ℃/W | Note B: mounted on a 1 in 2 pad of 2oz copper | 1 |
| Junction and Storage Temperature Range | TJ ,TSTG | -55 | | 150 | ℃ | | 1 |
| Drain-Source Breakdown Voltage | BVDSS | -30 | | | V | VGS=0V, ID=-250μA | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | -1 | μA | VDS=-30V,VGS=0V | 2 |
| Gate-Body Leakage Current | IGSS | -100 | | 100 | nA | VGS=±20V, VDS=0V | 2 |
| Gate Threshold Voltage | VGS(th) | -1 | -1.5 | -2.5 | V | VDS= VGS, ID=-250μA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 20 | 25 | mΩ | VGS=-10V, ID=-7A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 30 | 40 | mΩ | VGS=-4.5V, ID=-5A | 2 |
| Diode Forward Voltage | VSD | | | -1.2 | V | IS=-7A,VGS=0V | 2 |
| Input Capacitance | Ciss | | 1488 | | pF | VDS=-15V,VGS=0V,f=1MHZ | 2 |
| Output Capacitance | Coss | | 178 | | pF | VDS=-15V,VGS=0V,f=1MHZ | 2 |
| Reverse Transfer Capacitance | Crss | | 164 | | pF | VDS=-15V,VGS=0V,f=1MHZ | 2 |
| Total Gate Charge | Qg | | 28.44 | | nC | VGS=-10V,VDS=-15V,ID=-7.1A | 2 |
| Gate-Source Charge | Qgs | | 5.25 | | nC | VGS=-10V,VDS=-15V,ID=-7.1A | 2 |
| Gate-Drain Charge | Qgd | | 5.17 | | nC | VGS=-10V,VDS=-15V,ID=-7.1A | 2 |
| Reverse Recovery Charge | Qrr | | 5.3 | | | IF=-5A, di/dt=100A/us | 2 |
| Reverse Recovery Time | trr | | 14 | | ns | IF=-5A, di/dt=100A/us | 2 |
| Turn-on Delay Time | tD(on) | | 10 | | ns | VGS=-10V, VDS=-15V, ID=-7.1A RGEN=2.5Ω | 2 |
| Turn-on Rise Time | tr | | 44 | | ns | VGS=-10V, VDS=-15V, ID=-7.1A RGEN=2.5Ω | 2 |
| Turn-off Delay Time | tD(off) | | 54 | | ns | VGS=-10V, VDS=-15V, ID=-7.1A RGEN=2.5Ω | 2 |
| Turn-off Fall Time | tf | | 58 | | ns | VGS=-10V, VDS=-15V, ID=-7.1A RGEN=2.5Ω | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | mounting surface of the drain pins. RθJC is guaranteed by design, while RθJA is determined by the board design. The maximum rating presented here is based on mounting on a 1 in 2 pad of 2oz copper. | 2 |
## CAD (KiCad official)
- Symbol: `SL4813A`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `sl4813a-etched.step` / `sl4813a-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sl4813a.step` / `sl4813a.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Slkor SLKORMICRO Elec datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590230172743479296) (5 pp, sha256 `312361d6da68706c`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sl4813a-datasheet.pdf)