component
SK6513SD4-50
Public Made by Adomby adom
Suntek Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN1x1-4. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SK6513SD4-50
Suntek · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN1x1-4
SK6513SD4-50 from Suntek, in a DFN1x1-4. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Output pin of the regulator; the datasheet specifies a 300 mA maximum load current (IOUT 0 to 300 mA). |
| 2 | GND | power_in | Ground connection for the device. |
| 3 | EN | input | Enable control input, active high; the datasheet lists an EN input high threshold of 1.2 V and a low threshold of 0.4 V, and the EN pin is provided on the DFN1x1-4 package. |
| 4 | IN | power_in | Supply input pin; the operating input voltage range is 2.5 V to 36 V, with an absolute maximum input voltage of 0 to 44 V. |
| 5 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Suntek |
| Package | DFN1x1-4 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 0 | 44 | V | 3 | ||
| Output Voltage | VOUT | 0.8 | 6 | V | 3 | ||
| Chip Enable Input | VEN | -0.3 | 44 | V | 3 | ||
| Maximum Junction Temperature | TJ(MAX) | 150 | °C | 3 | |||
| Storage Temperature | TSTG | -55 | 150 | °C | 3 | ||
| ESD Human Body Model capability | HBM | 2000 | V | EIA/JESD22-A114 | 3 | ||
| ESD Charged Device Model capability | CDM | 1500 | V | JESD22-C101 | 3 | ||
| Latch up Current Maximum Rating | ILU | 200 | mA | JEDEC78 | 3 | ||
| Input Voltage | VIN | 2.5 | 36 | V | 3 | ||
| Output Current | IOUT | 0 | 300 | mA | 3 | ||
| Operating Ambient Temperature | TA | -40 | 85 | °C | 3 | ||
| Effective Input Ceramic Capacitor Value | CIN | 1 | 10 | μF | 3 | ||
| Effective Output Ceramic Capacitor Value | COUT | 1 | 10 | μF | 3 | ||
| Input and Output Capacitor Equivalent Series Resistance | ESR | 5 | 100 | mΩ | 3 | ||
| Thermal Resistance, Junction-to-Air (DFN-4L) | RθJA | 250 | °C/W | DFN-4L package | 3 | ||
| Power Dissipation @25°C (DFN-4L) | 500 | mW | DFN-4L package, @25°C, PCB 40mm x 40mm (2 layer), 1OZ copper | 3 | |||
| Operating Input Voltage | VIN | 36 | V | 4 | |||
| Line Regulation | RegLINE | 0.05 | 0.2 | %/V | 2.5V ≤ VIN ≤ 36V, IOUT = 10mA | 4 | |
| Load Regulation | RegLOAD | 40 | mV | 1mA ≤ IOUT ≤ 300mA, VIN = VOUT + 2V | 4 | ||
| Current Limit | ILMT | 300 | mA | VIN = VOUT + 2V | 4 | ||
| Quiescent Current | IQ | 2.5 | 4.5 | μA | IOUT = 0mA | 4 | |
| Standby Current | IQ_OFF | 0.1 | 1 | μA | VEN = 0V, TA = 25°C | 4 | |
| EN Pin Threshold Voltage High | VENH | 1.2 | V | EN Input Voltage “H” | 4 | ||
| EN Pin Threshold Voltage Low | VENL | 0.4 | V | EN Input Voltage “L” | 4 | ||
| EN Pin Current | IEN | 1 | μA | VEN = 0V to 36V | 4 | ||
| Power Supply Rejection Ratio | PSRR | 60 | dB | VIN = VOUT + 1V, IOUT = 20mA, f = 1 kHz | 4 | ||
| Output Noise Voltage | eN | 100 | μVRMS | VIN = VOUT + 2V, IOUT = 1mA, f = 10Hz to 100kHz, VOUT = 3V, COUT = 1μF | 4 | ||
| Thermal Shutdown Temperature | TSD | 155 | ℃ | Temperature increasing from TA = +25°C | 4 | ||
| Thermal Shutdown Hysteresis | TSDH | 30 | ℃ | Temperature falling from TSD | 4 |
CAD (KiCad official)
- Symbol:
SK6513SD4-50 - Footprint:
Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm - 3D model: DFN1x1-4 (KiCad packages3D, STEP)
- 3D model files:
sk6513sd4-50-etched.step/sk6513sd4-50-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sk6513sd4-50.step/sk6513sd4-50.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Suntek datasheet (12 pp, sha256
01cf747623c54657, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SK6513SD4-50
**Suntek** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN1x1-4
SK6513SD4-50 from Suntek, in a DFN1x1-4. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Output pin of the regulator; the datasheet specifies a 300 mA maximum load current (IOUT 0 to 300 mA). |
| 2 | GND | power_in | Ground connection for the device. |
| 3 | EN | input | Enable control input, active high; the datasheet lists an EN input high threshold of 1.2 V and a low threshold of 0.4 V, and the EN pin is provided on the DFN1x1-4 package. |
| 4 | IN | power_in | Supply input pin; the operating input voltage range is 2.5 V to 36 V, with an absolute maximum input voltage of 0 to 44 V. |
| 5 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Suntek |
| Package | DFN1x1-4 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 0 | | 44 | V | | 3 |
| Output Voltage | VOUT | 0.8 | | 6 | V | | 3 |
| Chip Enable Input | VEN | -0.3 | | 44 | V | | 3 |
| Maximum Junction Temperature | TJ(MAX) | | | 150 | °C | | 3 |
| Storage Temperature | TSTG | -55 | | 150 | °C | | 3 |
| ESD Human Body Model capability | HBM | | | 2000 | V | EIA/JESD22-A114 | 3 |
| ESD Charged Device Model capability | CDM | | | 1500 | V | JESD22-C101 | 3 |
| Latch up Current Maximum Rating | ILU | | | 200 | mA | JEDEC78 | 3 |
| Input Voltage | VIN | 2.5 | | 36 | V | | 3 |
| Output Current | IOUT | 0 | | 300 | mA | | 3 |
| Operating Ambient Temperature | TA | -40 | | 85 | °C | | 3 |
| Effective Input Ceramic Capacitor Value | CIN | 1 | | 10 | μF | | 3 |
| Effective Output Ceramic Capacitor Value | COUT | 1 | | 10 | μF | | 3 |
| Input and Output Capacitor Equivalent Series Resistance | ESR | 5 | | 100 | mΩ | | 3 |
| Thermal Resistance, Junction-to-Air (DFN-4L) | RθJA | | 250 | | °C/W | DFN-4L package | 3 |
| Power Dissipation @25°C (DFN-4L) | | | 500 | | mW | DFN-4L package, @25°C, PCB 40mm x 40mm (2 layer), 1OZ copper | 3 |
| Operating Input Voltage | VIN | | | 36 | V | | 4 |
| Line Regulation | RegLINE | | 0.05 | 0.2 | %/V | 2.5V ≤ VIN ≤ 36V, IOUT = 10mA | 4 |
| Load Regulation | RegLOAD | | | 40 | mV | 1mA ≤ IOUT ≤ 300mA, VIN = VOUT + 2V | 4 |
| Current Limit | ILMT | | 300 | | mA | VIN = VOUT + 2V | 4 |
| Quiescent Current | IQ | | 2.5 | 4.5 | μA | IOUT = 0mA | 4 |
| Standby Current | IQ_OFF | | 0.1 | 1 | μA | VEN = 0V, TA = 25°C | 4 |
| EN Pin Threshold Voltage High | VENH | | 1.2 | | V | EN Input Voltage “H” | 4 |
| EN Pin Threshold Voltage Low | VENL | | 0.4 | | V | EN Input Voltage “L” | 4 |
| EN Pin Current | IEN | | | 1 | μA | VEN = 0V to 36V | 4 |
| Power Supply Rejection Ratio | PSRR | | 60 | | dB | VIN = VOUT + 1V, IOUT = 20mA, f = 1 kHz | 4 |
| Output Noise Voltage | eN | | 100 | | μVRMS | VIN = VOUT + 2V, IOUT = 1mA, f = 10Hz to 100kHz, VOUT = 3V, COUT = 1μF | 4 |
| Thermal Shutdown Temperature | TSD | | 155 | | ℃ | Temperature increasing from TA = +25°C | 4 |
| Thermal Shutdown Hysteresis | TSDH | | 30 | | ℃ | Temperature falling from TSD | 4 |
## CAD (KiCad official)
- Symbol: `SK6513SD4-50`
- Footprint: `Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm`
- 3D model: DFN1x1-4 (KiCad packages3D, STEP)
- 3D model files: `sk6513sd4-50-etched.step` / `sk6513sd4-50-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sk6513sd4-50.step` / `sk6513sd4-50.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Suntek datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8610872238560464896) (12 pp, sha256 `01cf747623c54657`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sk6513sd4-50-datasheet.pdf)