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SJA1000M

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HGSEMI CAN Transceivers, SOP-28. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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SJA1000M

HGSEMI · CAN Transceivers · SOP-28

SJA1000M from HGSEMI, in a SOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AD7-AD0 bidirectional Multiplexed address/data bus; the datasheet gives this group of pins (2, 1, 28-23) without a bit-by-bit mapping, so individual bit assignment is not stated in the text.
2 AD7-AD0 bidirectional Multiplexed address/data bus; the datasheet gives this group of pins (2, 1, 28-23) without a bit-by-bit mapping, so individual bit assignment is not stated in the text.
3 ALE/AS input Address latch enable input in Intel mode and address strobe input in Motorola mode; low-level input limit VIL1 is 0.8 V max and high-level input VIH1 is 2.0 V min (VDD+0.5 V max).
4 /CS input Chip select input; a low level enables access to the SJA1000.
5 /RD /E input Read strobe from the microcontroller in Intel mode (/RD), or enable strobe in Motorola mode (E).
6 /WR input Write strobe from the microcontroller in Intel mode (/WR), or read/write select in Motorola mode (R/WR).
7 CLKOUT output Clock output to the microcontroller, derived from the internal oscillator and programmable by the clock divider register; the clock-off bit in the clock control register can disable this pin.
8 VSS1 power_in Ground for the logic circuitry.
9 XTAL1 input Input to the oscillator amplifier circuit where an external oscillator signal is applied; must be connected to VSS1 through a 15 pF capacitor (note 1), and the oscillator frequency is specified up to 24 MHz.
10 XTAL2 output Output of the oscillator amplifier circuit, left unconnected when an external oscillator signal is used; must be connected to VSS1 through a 15 pF capacitor (note 1).
11 MODE input Mode select input: high (1) selects Intel mode and low (0) selects Motorola mode.
12 VDD3 power_in 5 V supply voltage for the output drivers (VDD = 5 V ±10%, 4.5 V to 5.5 V).
13 TX0 output Output from CAN output driver 0 to the physical bus line; peak sink current IOT is limited to 100 ms duration, and average output current per TX output must not exceed 10 mA.
14 TX1 output Output from CAN output driver 1 to the physical bus line; peak sink current IOT is limited to 100 ms duration, and average output current per TX output must not exceed 10 mA.
15 VSS3 power_in Ground for the output drivers.
16 /INT output Open-drain active-low interrupt output to the microcontroller, asserted when internal interrupt register bits are set; it is wire-ORed with other /INT pins in the system and a low level can wake the IC from sleep mode.
17 /RST input Active-low reset input for the CAN interface; connect through a capacitor to VSS for reset and through a resistor to VDD for automatic power-on reset (example: C = 1 nF, R = 50 kΩ).
18 VDD2 power_in 5 V supply voltage for the input comparator.
19 RX0 input Input from the physical CAN bus to the input comparator; a dominant level wakes the SJA1000 from sleep mode, and when CBP is set this comparator is bypassed so only RX0 is active (weak level read as high, dominant as low).
20 RX1 input Input from the physical CAN bus to the input comparator; when RX1 is higher than RX0 the bus is read as dominant, otherwise as recessive, and it is not used when the CBP bit of the clock divider register is set.
21 VSS2 power_in Ground for the input comparator.
22 VDD1 power_in 5 V supply voltage for the logic circuitry.
23 AD7-AD0 bidirectional Multiplexed address/data bus; the datasheet gives this group of pins (2, 1, 28-23) without a bit-by-bit mapping, so individual bit assignment is not stated in the text.
24 AD7-AD0 bidirectional Multiplexed address/data bus; the datasheet gives this group of pins (2, 1, 28-23) without a bit-by-bit mapping, so individual bit assignment is not stated in the text.
25 AD7-AD0 bidirectional Multiplexed address/data bus; the datasheet gives this group of pins (2, 1, 28-23) without a bit-by-bit mapping, so individual bit assignment is not stated in the text.
26 AD7-AD0 bidirectional Multiplexed address/data bus; the datasheet gives this group of pins (2, 1, 28-23) without a bit-by-bit mapping, so individual bit assignment is not stated in the text.
27 AD7-AD0 bidirectional Multiplexed address/data bus; the datasheet gives this group of pins (2, 1, 28-23) without a bit-by-bit mapping, so individual bit assignment is not stated in the text.
28 AD7-AD0 bidirectional Multiplexed address/data bus; the datasheet gives this group of pins (2, 1, 28-23) without a bit-by-bit mapping, so individual bit assignment is not stated in the text.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package SOP-28
Category Interface
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD VDD 4.5 5.5 V 5
Operating current IDD 15 mA fOSC=24MHz;注 1 5
Sleep mode current Ism 40 uA 振荡器非激活状态; 注 2 5
Low-level input voltage, pins ALE/AS, /CS, (/RD)/E, /WR, MODE VIL1 -0.5 0.8 V 5
Low-level input voltage, pins XTAL1 and /INT VIL2 0.3 V max printed as 0.3 VDD (fraction of VDD; see review_required) 5
Low-level input voltage, pins /RST, AD0-AD7, RX0 VIL3 -0.5 0.6 V 5
High-level input voltage, pins ALE/AS, /CS, (/RD)/E, /WR, MODE VIH1 2 0.5 V max printed as VDD+0.5 V (numeric part 0.5 is an offset above VDD; see review_required) 5
High-level input voltage, pins XTAL1 and /INT VIH2 0.7 V min printed as 0.7VDD (fraction of VDD; see review_required) 5
High-level input voltage, pins /RST, AD0-AD7, RX0 VIH3 2.4 0.5 V max printed as VDD+0.5 V (numeric part 0.5 is an offset above VDD; see review_required) 5
Input hysteresis, pins /RST, AD0-AD7, RX0 hysRST 500 mA 注 5 (unit printed as mA; see review_required) 5
Input leakage current, all pins except XTAL1, RX0, RX1 ILI -2 2 uA 0.45V<VI(D)<VDD; 注 3 5
Low-level output voltage, pins AD0-AD7, CLKOUT, /INT VOL 0.4 V IOL=4Ma 5
High-level output voltage, pins AD0-AD7, CLKOUT, /INT VOH 0.4 V IOH=-4mA; min printed as VDD-0.4 V (see review_required) 5
Differential input threshold voltage, CAN comparator Vth(I)(diff) 32 mV VDD=5V 10%; 1.4V<VI(RX)<VDD-1.4V; 注 4 和 6 5
Hysteresis voltage, CAN comparator Vhys 8 30 mV 5
Input current, CAN comparator II -400 400 nA 5
Low-level output voltage, pins TX0 and TX1 VOL(TX) 0.05 V VDD=5V 10%; IO=1.2mA; 注 6 5
Low-level output voltage, pins TX0 and TX1 VOL(TX) 0.4 V VDD=5V 10%; IO=10mA; 注 6 5
High-level output voltage, pins TX0 and TX1 VOH(TX) 0.05 V VDD=5V 10%; IO=1.2mA; 注 6; min printed as VDD-0.05 (see review_required) 5
High-level output voltage, pins TX0 and TX1 VOH(TX) 0.4 V VDD=5V 10%; IO=10mA; 注 6; min printed as VDD-0.4 (see review_required) 5
Oscillator frequency fOSC 24 MHz 6
Address setup time to ALE/AS low tSU(A-AL) 8 ns 6
ALE low hold time after address th(AL-A) 2 ns 6
ALE/AS pulse width tW(AL) 8 ns 6
/RD low to output valid data tRLQV 50 ns Intel 模式 6
E high to output valid data tEHQV 50 ns Motorola 模式 6
/RD high to data floating tRHDZ 30 ns Intel 模式 6
E low to data floating tELDZ 30 ns Motorola 模式 6
Input data valid to /WR high tDVWH 8 ns Intel 模式 6
Data hold time after /WR high tWHDX 8 ns Intel 模式 6
/WR high to next ALE high tWHLH 15 ns 6
E low to next AS high tELAH 15 ns Motorola 模式 6
E low input data setup time tsu(I)(D-EL) 8 ns Motorola 模式 6
E low input data hold time th(I)(EL-D) 8 ns Motorola 模式 6
ALE low to /WR low tLLWL 10 ns Intel 模式 6
ALE low to /RD low tLLRL 10 ns Intel 模式 6
AS low to E high tLLEH 10 ns Motorola 模式 6
RD/WR to E high setup time tsu(R-EH) 5 ns Motorola 模式 6
/WR pulse width tW(W) 20 ns Intel 模式 6
/RD pulse width tW(R) 40 ns Intel 模式 6
E pulse width tW(E) 40 ns Motorola 模式 6
/CS low to /WR low tCLWL 0 ns Intel 模式 6
/CS low to /RD low tCLRL 0 ns Intel 模式 6
/CS low to E high tCLEH 0 ns Motorola 模式 6
/WR high to /CS high tWHCH 0 ns Intel 模式 6
/RD high to /CS high tRHCH 0 ns Intel 模式 6
E low to /CS high tELCH 0 ns Motorola 模式 6
/RST pulse width tW(RST) 100 ns 6
Sum of input and output delay, CAN comparator/output driver tSD 40 ns VDD=5±10%; VDIF=±32mV; 1.4V<VI(RX)<VDD-1.4V; 注 2 6
Supply voltage VDD (absolute maximum, referenced to VSS) VDD -0.5 6.5 V 4
Input/output current, all pins except TX0 and TX1 II,IO -4 4 mA 4
Sum of sink current, TX0 and TX1 IOT(sink) 30 mA 注 1 4
Sum of source current, TX0 and TX1 IOT(source) -20 mA 注 1 4
Ambient operating temperature Tamb -40 125 ℃ 4
Storage temperature Tstg -65 150 ℃ 4
Total power dissipation Ptot 1 W 4
ESD discharge per pin, human body model Vesd -1500 1500 V 注 3; 人体模型 4
ESD discharge per pin, machine model Vesd -200 200 V 注 4; 机器模型 4

CAD (KiCad official)

  • Symbol: SJA1000M
  • Footprint: Package_SO:SOP-28_8.4x18.16mm_P1.27mm
  • 3D model: SOP-28 (KiCad packages3D, STEP)
  • 3D model files: sja1000m-etched.step / sja1000m-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sja1000m.step / sja1000m.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (8 pp, sha256 808e32a5159a5748, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF