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SIT8008BI-21-YYS-12.000000
Public Made by Adomby adom
SiTime Programmable Oscillators, SMD3225-4P. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SIT8008BI-21-YYS-12.000000
SiTime · Programmable Oscillators · SMD3225-4P
SIT8008BI-21-YYS-12.000000 from SiTime, in a SMD3225-4P. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE/ST/NC | input | Factory-programmed as Output Enable (low puts OUT in high-Z, high gives the specified frequency), Standby (low puts the device in sleep at reduced current with output weakly pulled low, high resumes within 5 ms), or No Connect (no function); with OE or ST, a pull-up of 10 kΩ or less is recommended if the pin is not externally driven, with VIH of 70% Vdd and VIL of 30% Vdd. |
| 2 | GND | power_in | Electrical ground; a 0.1 µF or higher capacitor between VDD and GND is required. |
| 3 | OUT | output | Oscillator LVCMOS/HCMOS clock output at the specified frequency, with 20%-80% rise/fall time and 45-55% duty cycle per Table 1. |
| 4 | VDD | power_in | Power supply voltage, which must be within the rated range for the factory-programmed supply option; a 0.1 µF or higher capacitor to GND is required. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SiTime |
| Package | SMD3225-4P |
| Category | Crystals, Oscillators, Resonators |
| Pins | 4 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Frequency Range | f | 1 | 110 | MHz | 1 | ||
| Supply Voltage (Vdd_YY option) | Vdd_YY | 1.62 | 3.63 | V | 1 | ||
| Operating Temperature Range (Industrial) | T_use | -40 | 85 | °C | Industrial | 1 | |
| Current Consumption | Idd | 3.8 | 4.5 | mA | No load condition, f = 20 MHz, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY | 1 | |
| OE Disable Current | I_OD | 4.2 | mA | Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY. OE = GND, Output in high-Z state | 1 | ||
| Standby Current | I_std | 2.1 | 4.3 | µA | ST = GND, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY. Output is weakly pulled down | 1 | |
| Duty Cycle | DC | 45 | 55 | % | All Vdds. See Duty Cycle definition in Figure 3 and Footnote 6 | 2 | |
| Rise/Fall Time (20% to 80%) | Tr, Tf | 2.7 | ns | 20% - 80% Vdd_YY | 2 | ||
| Output High Voltage | VOH | 90 | % Vdd | IOH = -4 mA (Vdd_3.0 and Vdd_3.3); IOH = -3 mA (Vdd_2.8 and Vdd_2.5); IOH = -2 mA (Vdd_1.8) | 2 | ||
| Output Low Voltage | VOL | 10 | % Vdd | IOL = 4 mA (Vdd_3.0 and Vdd_3.3); IOL = 3 mA (Vdd_2.8 and Vdd_2.5); IOL = 2 mA (Vdd_1.8) | 2 | ||
| Input High Voltage | VIH | 70 | % Vdd | Pin 1, OE or ST | 2 | ||
| Input Low Voltage | VIL | 30 | % Vdd | Pin 1, OE or ST | 2 | ||
| Input Pull-up Impedance | Z_in | 50 | 87 | 150 | kΩ | Pin 1, OE logic high or logic low, or ST logic high | 2 |
| Input Pull-up Impedance (ST logic low) | Z_in | 2 | MΩ | Pin 1, ST logic low | 2 | ||
| Startup Time | T_start | 5 | ms | Measured from the time Vdd reaches its rated minimum value | 2 | ||
| Enable/Disable Time | T_oe | 130 | ns | f = 110 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles | 2 | ||
| Resume Time | T_resume | 5 | ms | Measured from the time ST pin crosses 50% threshold | 2 | ||
| RMS Period Jitter | T_jitt | 3.3 | ps | f = 75 MHz, Vdd_YY | 2 | ||
| Peak-to-peak Period Jitter | T_pk | 12 | 25 | ps | f = 75 MHz, Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY | 2 | |
| RMS Phase Jitter (random) | T_phj | 1.4 | ps | f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz. Vdd_YY | 2 | ||
| RMS Phase Jitter (random) | T_phj | 2.3 | ps | f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz. Vdd_YY | 2 | ||
| Storage Temperature | -65 | 150 | °C | 3 | |||
| Supply Voltage (Vdd) | Vdd | -0.5 | 4 | V | 3 | ||
| Electrostatic Discharge | 2000 | V | 3 | ||||
| Soldering Temperature | 260 | °C | Follow standard Pb free soldering guidelines | 3 | |||
| Junction Temperature | 150 | °C | 3 | ||||
| Thermal Resistance Junction-to-Ambient (3225 package) | θJA | 109 | °C/W | 4 Layer Board | 3 | ||
| Thermal Resistance Junction-to-Ambient (3225 package) | θJA | 212 | °C/W | 2 Layer Board | 3 | ||
| Thermal Resistance Junction-to-Case Bottom (3225 package) | θJC | 27 | °C/W | Bottom | 3 | ||
| Maximum Operating Junction Temperature | 95 | °C | Max operating ambient temperature 85°C | 3 | |||
| Maximum Operating Junction Temperature | 80 | °C | Max operating ambient temperature 70°C | 3 |
CAD (KiCad official)
- Symbol:
SIT8008BI-21-YYS-12.000000 - Footprint:
Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm - 3D model: SMD3225-4P (KiCad packages3D, STEP)
- 3D model files:
sit8008bi-21-yys-12-000000-etched.step/sit8008bi-21-yys-12-000000-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sit8008bi-21-yys-12-000000.step/sit8008bi-21-yys-12-000000.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SiTime datasheet (18 pp, sha256
fcdbddbb6ff5c9c4, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SIT8008BI-21-YYS-12.000000
**SiTime** · Programmable Oscillators · SMD3225-4P
SIT8008BI-21-YYS-12.000000 from SiTime, in a SMD3225-4P. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE/ST/NC | input | Factory-programmed as Output Enable (low puts OUT in high-Z, high gives the specified frequency), Standby (low puts the device in sleep at reduced current with output weakly pulled low, high resumes within 5 ms), or No Connect (no function); with OE or ST, a pull-up of 10 kΩ or less is recommended if the pin is not externally driven, with VIH of 70% Vdd and VIL of 30% Vdd. |
| 2 | GND | power_in | Electrical ground; a 0.1 µF or higher capacitor between VDD and GND is required. |
| 3 | OUT | output | Oscillator LVCMOS/HCMOS clock output at the specified frequency, with 20%-80% rise/fall time and 45-55% duty cycle per Table 1. |
| 4 | VDD | power_in | Power supply voltage, which must be within the rated range for the factory-programmed supply option; a 0.1 µF or higher capacitor to GND is required. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SiTime |
| Package | SMD3225-4P |
| Category | Crystals, Oscillators, Resonators |
| Pins | 4 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Frequency Range | f | 1 | | 110 | MHz | | 1 |
| Supply Voltage (Vdd_YY option) | Vdd_YY | 1.62 | | 3.63 | V | | 1 |
| Operating Temperature Range (Industrial) | T_use | -40 | | 85 | °C | Industrial | 1 |
| Current Consumption | Idd | | 3.8 | 4.5 | mA | No load condition, f = 20 MHz, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY | 1 |
| OE Disable Current | I_OD | | | 4.2 | mA | Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY. OE = GND, Output in high-Z state | 1 |
| Standby Current | I_std | | 2.1 | 4.3 | µA | ST = GND, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY. Output is weakly pulled down | 1 |
| Duty Cycle | DC | 45 | | 55 | % | All Vdds. See Duty Cycle definition in Figure 3 and Footnote 6 | 2 |
| Rise/Fall Time (20% to 80%) | Tr, Tf | | | 2.7 | ns | 20% - 80% Vdd_YY | 2 |
| Output High Voltage | VOH | 90 | | | % Vdd | IOH = -4 mA (Vdd_3.0 and Vdd_3.3); IOH = -3 mA (Vdd_2.8 and Vdd_2.5); IOH = -2 mA (Vdd_1.8) | 2 |
| Output Low Voltage | VOL | | | 10 | % Vdd | IOL = 4 mA (Vdd_3.0 and Vdd_3.3); IOL = 3 mA (Vdd_2.8 and Vdd_2.5); IOL = 2 mA (Vdd_1.8) | 2 |
| Input High Voltage | VIH | 70 | | | % Vdd | Pin 1, OE or ST | 2 |
| Input Low Voltage | VIL | | | 30 | % Vdd | Pin 1, OE or ST | 2 |
| Input Pull-up Impedance | Z_in | 50 | 87 | 150 | kΩ | Pin 1, OE logic high or logic low, or ST logic high | 2 |
| Input Pull-up Impedance (ST logic low) | Z_in | 2 | | | MΩ | Pin 1, ST logic low | 2 |
| Startup Time | T_start | | | 5 | ms | Measured from the time Vdd reaches its rated minimum value | 2 |
| Enable/Disable Time | T_oe | | | 130 | ns | f = 110 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles | 2 |
| Resume Time | T_resume | | | 5 | ms | Measured from the time ST pin crosses 50% threshold | 2 |
| RMS Period Jitter | T_jitt | | | 3.3 | ps | f = 75 MHz, Vdd_YY | 2 |
| Peak-to-peak Period Jitter | T_pk | | 12 | 25 | ps | f = 75 MHz, Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY | 2 |
| RMS Phase Jitter (random) | T_phj | | | 1.4 | ps | f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz. Vdd_YY | 2 |
| RMS Phase Jitter (random) | T_phj | | | 2.3 | ps | f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz. Vdd_YY | 2 |
| Storage Temperature | | -65 | | 150 | °C | | 3 |
| Supply Voltage (Vdd) | Vdd | -0.5 | | 4 | V | | 3 |
| Electrostatic Discharge | | | | 2000 | V | | 3 |
| Soldering Temperature | | | | 260 | °C | Follow standard Pb free soldering guidelines | 3 |
| Junction Temperature | | | | 150 | °C | | 3 |
| Thermal Resistance Junction-to-Ambient (3225 package) | θJA | | 109 | | °C/W | 4 Layer Board | 3 |
| Thermal Resistance Junction-to-Ambient (3225 package) | θJA | | 212 | | °C/W | 2 Layer Board | 3 |
| Thermal Resistance Junction-to-Case Bottom (3225 package) | θJC | | 27 | | °C/W | Bottom | 3 |
| Maximum Operating Junction Temperature | | | | 95 | °C | Max operating ambient temperature 85°C | 3 |
| Maximum Operating Junction Temperature | | | | 80 | °C | Max operating ambient temperature 70°C | 3 |
## CAD (KiCad official)
- Symbol: `SIT8008BI-21-YYS-12.000000`
- Footprint: `Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm`
- 3D model: SMD3225-4P (KiCad packages3D, STEP)
- 3D model files: `sit8008bi-21-yys-12-000000-etched.step` / `sit8008bi-21-yys-12-000000-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sit8008bi-21-yys-12-000000.step` / `sit8008bi-21-yys-12-000000.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [SiTime datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590933010332540928) (18 pp, sha256 `fcdbddbb6ff5c9c4`, retrieved 2026-10-15, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sit8008bi-21-yys-12-000000-datasheet.pdf)