# SIT65HVD75DGK

**SIT** · RS-485 / RS-422 ICs · MSOP-8

SIT65HVD75DGK from SIT, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RO | output | Receiver output: with /RE low, RO is high when A-B ≥ -10 mV and low when A-B ≤ -200 mV; RO is high-impedance when /RE is high. |
| 2 | /RE | input | Receiver output enable, active low: a low enables RO, a high disables the receiver output (high-impedance), and /RE high with DE low puts the device into low-power shutdown. |
| 3 | DE | input | Driver output enable: a high enables the driver outputs A and B, a low sets them to high-impedance; with /RE high and DE low the device enters shutdown. |
| 4 | DI | input | Driver input: when DE is high, a low on DI drives A low and B high, and a high on DI drives A high and B low. |
| 5 | GND | power_in | Ground reference for the device; the datasheet recommends connecting the MSOP8/VSSOP8 back metal pad to ground. |
| 6 | A | bidirectional | Non-inverting receiver input and driver output on the RS-485 bus, with a bus common-mode range of -7 V to +12 V for receiver thresholds and bus fault tolerance of ±15 V. |
| 7 | B | bidirectional | Inverting receiver input and driver output on the RS-485 bus, with a bus common-mode range of -7 V to +12 V for receiver thresholds and bus fault tolerance of ±15 V. |
| 8 | VCC | power_in | Supply pin; the operating supply range is 3.0 V to 5.5 V, with an absolute maximum of +7 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | SIT |
| Package | MSOP-8 |
| Category | Interface |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC |  |  | 7 | V |  | 3 |
| Control port voltage /RE, DE, DI |  | -0.3 |  |  | V |  | 3 |
| Bus pin input voltage A, B |  | -15 |  | 15 | V |  | 3 |
| Receiver output voltage RO |  | -0.3 |  |  | V |  | 3 |
| Operating temperature range | TA | -40 |  | 125 | ℃ |  | 3 |
| Storage temperature range | Tstg | -60 |  | 150 | ℃ |  | 3 |
| Soldering temperature range |  |  |  | 300 | ℃ |  | 3 |
| Driver differential output (no load) | VOD1 | 2.5 |  | 5.5 | V | No load | 4 |
| Driver differential output | VOD2 | 1.5 | 1.8 |  | V | Fig 2, RL=54Ω, VCC=3.3V | 4 |
| Driver differential output | VOD2 | 1.5 | 3 |  | V | Fig 2, RL=54Ω, VCC=5V | 4 |
| Change in differential output voltage magnitude | ΔVOD |  |  | 0.2 | V | Fig 2, RL=54Ω | 4 |
| Change in common-mode output voltage magnitude | ΔVOC |  |  | 0.2 | V | Fig 2, RL=54Ω | 4 |
| High-level input voltage | VIH | 2 |  |  | V | DE, DI, /RE | 4 |
| Low-level input voltage | VIL |  |  | 0.8 | V | DE, DI, /RE | 4 |
| Logic input current | IIN1 | -2 |  | 2 | µA | DE, DI, /RE | 4 |
| Driver output short-circuit current, shorted to high | IOSD1 |  |  | 250 | mA | Shorted to 0V~12V | 4 |
| Driver output short-circuit current, shorted to low | IOSD2 | -250 |  |  | mA | Shorted to -7V~0V | 4 |
| Input current (A, B) | IIN2 | 500 |  | 1000 | µA | DE=0V, VCC=0 or 5V, VIN=12V | 4 |
| Input current (A, B) | IIN2 | -800 |  | -300 | µA | DE=0V, VCC=0 or 5V, VIN=-7V | 4 |
| Positive-going input threshold voltage | VIT+ |  |  | -10 | mV | -7V≤VCM≤12V | 4 |
| Negative-going input threshold voltage | VIT- | -200 |  |  | mV | -7V≤VCM≤12V | 4 |
| Input hysteresis voltage | Vhys | 10 |  | 30 | mV | -7V≤VCM≤12V | 4 |
| Low-level output voltage | VOL |  |  | 0.4 | V | IOUT=+2.5mA, VID=-200mV | 5 |
| Tri-state input leakage current | IOZR | -1 |  | 1 | µA | 0.4V<VO<2.4V | 5 |
| Receiver input resistance | RIN | 12 |  |  | kΩ | -7V≤VCM≤12V | 5 |
| Receiver short-circuit current | IOSR | -8 |  | 8 | mA | 0V≤VO≤VCC | 5 |
| Receiver short-circuit current | IOSR | -90 |  | 90 | mA | 0V≤VO≤VCC | 5 |
| Supply current, driver and receiver disabled | ICC1 |  | 240 | 650 | µA | /RE=0V, DE=0V, VCC=3.3V | 5 |
| Supply current, driver and receiver disabled | ICC1 |  | 270 | 750 | µA | /RE=0V, DE=0V, VCC=5V | 5 |
| Supply current, driver and receiver enabled | ICC2 |  | 360 | 650 | µA | /RE=VCC, DE=VCC, VCC=3.3V | 5 |
| Supply current, driver and receiver enabled | ICC2 |  | 400 | 750 | µA | /RE=VCC, DE=VCC, VCC=5V | 5 |
| Shutdown supply current | ISHDN |  | 0.2 | 10 | µA | /RE=VCC, DE=0V, VCC=3.3V | 5 |
| Driver differential output delay | tDD |  | 15 | 32 | ns | RL=60Ω, CL=100pF; see Fig 3 and 4 | 5 |
| Driver differential output transition time | tTD |  | 9 | 20 | ns |  | 5 |
| Driver propagation delay, low to high | tPLH |  | 18 | 40 | ns | RL=27Ω; see Fig 3 and 4 | 5 |
| Driver propagation delay, high to low | tPHL |  | 18 | 40 | ns | RL=27Ω; see Fig 3 and 4 | 5 |
| Driver propagation delay skew | tPDS |  | 2 | 6 | ns | RL=27Ω; see Fig 3 and 4 | 5 |
| Driver enable to output high | tPZH |  | 16 | 45 | ns | RL=110Ω; see Fig 5 and 6 | 5 |
| Driver enable to output low | tPZL |  | 16 | 45 | ns | RL=110Ω; see Fig 5 and 6 | 5 |
| Driver input low to disable | tPLZ |  | 22 | 85 | ns | RL=110Ω; see Fig 5 and 6 | 6 |
| Driver input high to disable | tPHZ |  | 22 | 85 | ns | RL=110Ω; see Fig 5 and 6 | 6 |
| Driver enable to output high in shutdown | tPSH |  | 20 | 100 | ns | Shutdown; RL=110Ω; see Fig 5 and 6 | 6 |
| Driver enable to output low in shutdown | tPSL |  | 20 | 100 | ns | Shutdown; RL=110Ω; see Fig 5 and 6 | 6 |
| Receiver propagation delay, low to high | tRPLH |  | 35 | 60 | ns | CL=15pF; see Fig 7 and 8 | 6 |
| Receiver propagation delay, high to low | tRPHL |  | 35 | 60 | ns | CL=15pF; see Fig 7 and 8 | 6 |
| Receiver propagation delay skew | tRPDS |  | 3 | 8 | ns |  | 6 |
| Receiver enable to output low | tRPZL |  | 16 | 30 | ns | CL=15pF; see Fig 7 and 8 | 6 |
| Receiver enable to output high | tRPZH |  | 16 | 30 | ns | CL=15pF; see Fig 7 and 8 | 6 |
| Receiver output low to disable | tRPLZ |  | 30 | 50 | ns | CL=15pF; see Fig 7 and 8 | 6 |
| Receiver output high to disable | tRPHZ |  | 30 | 50 | ns | CL=15pF; see Fig 7 and 8 | 6 |
| Receiver enable to output high in shutdown | tRPSH |  | 150 | 500 | ns | Shutdown; CL=15pF; see Fig 7 and 8 | 6 |
| Receiver enable to output low in shutdown | tRPSL |  | 150 | 500 | ns | Shutdown; CL=15pF; see Fig 7 and 8 | 6 |
| Time to enter shutdown | tSHDN |  | 50 | 300 | ns | NOTE2: /RE=1, DE=0 | 6 |

## CAD (KiCad official)

- Symbol: `SIT65HVD75DGK`
- Footprint: `Package_SO:MSOP-8_3x3mm_P0.65mm`
- 3D model: MSOP-8 (KiCad packages3D, STEP)
- 3D model files: `sit65hvd75dgk-etched.step` / `sit65hvd75dgk-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sit65hvd75dgk.step` / `sit65hvd75dgk.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [SIT datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8765934064190795776) (21 pp, sha256 `332f127c8c57f9f5`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sit65hvd75dgk-datasheet.pdf)