# SIT65HVD234DR

**SIT** · CAN Transceivers · SOP-8

SIT65HVD234DR from SIT, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D | input | CAN transmit data input (LOW for dominant and HIGH for recessive bus states), also called TXD, and it is the driver input. |
| 2 | GND | power_in | Ground, which is the reference point for all voltages on the device. |
| 3 | VCC | power_in | Transceiver 3.3V supply voltage, with a supply range of 3 V to 3.6 V (VCC = 3.3V ±10%). |
| 4 | R | output | CAN receive data output (LOW for dominant and HIGH for recessive bus states), also called RXD, and it is the receiver output. |
| 5 | EN | input | Enable input: EN=1 gives normal operation (high speed or standby mode) and EN=0 puts the device into low power sleep mode, where the driver and receiver are not working. |
| 6 | CANL | bidirectional | Low level CAN bus line, rated for bus input or output voltage from -36 V to +36 V, with bus pin ESD protection exceeding ±16 kV HBM. |
| 7 | CANH | bidirectional | High level CAN bus line, rated for bus input or output voltage from -36 V to +36 V, with bus pin ESD protection exceeding ±16 kV HBM. |
| 8 | RS | input | Mode select: a strong pull down to GND selects high speed mode, a strong pull up to VCC selects low power standby mode, and a 10 kΩ to 100 kΩ pull down to GND selects slope control mode. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | SIT |
| Package | SOP-8 |
| Category | Interface |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | Vcc | 3 |  | 3.6 | V |  | 1 |
| CANH, CANL input or output voltage | Vcan | -36 |  | 36 | V |  | 1 |
| Bus differential voltage | Vdiff | 1.5 |  | 3 | V |  | 1 |
| Virtual junction temperature | Tj | -40 |  | 125 | ℃ |  | 1 |
| Supply voltage | VCC | -0.3 |  | 6 | V |  | 3 |
| DC voltage on D/R pins | D, R | -0.5 |  |  | V |  | 3 |
| Voltage range at any bus terminal (CANH, CANL) | CANL, CANH | -36 |  | 36 | V |  | 3 |
| Transient voltage on pins CANH, CANL | Vtr | -40 |  | 40 | V | test with 100Ω, see Fig 10 | 3 |
| Receiver output current | IO | -11 |  | 11 | mA |  | 3 |
| Storage temperature | Tstg | -40 |  | 150 | ℃ |  | 3 |
| Virtual junction temperature | Tj | -40 |  | 125 | ℃ |  | 3 |
| Output voltage (Dominant), CANH | VO(D) | 2.45 |  |  | V | VI=0V, RS=0V, RL=60Ω (Fig1, Fig 2) | 4 |
| Output voltage (Dominant), CANL | VO(D) | 0.5 |  | 1.25 | V | VI=0V, RS=0V, RL=60Ω (Fig1, Fig 2) | 4 |
| Differential output voltage (Dominant) | VOD(D) | 1.5 | 2 | 3 | V | VI=0V, RS=0V, RL=60Ω (Fig 1) | 4 |
| Differential output voltage (Dominant) | VOD(D) | 1.2 | 2 | 3 | V | VI=0V, RL=60Ω, RS=0V (Fig 3) | 4 |
| Differential output voltage (Recessive) | VOD(R) | -0.12 |  | 0.012 | V | VI=3V, RS=0V | 4 |
| Differential output voltage (Recessive), no load | VOD(R) | -0.5 |  | 0.05 | V | VI=3V, RS=0V, NO LOAD | 4 |
| High-level input current | IIH | -30 |  | 30 | μA | VI=2V | 4 |
| Low-level input current | IIL | -30 |  | 30 | μA | VI=0.8V | 4 |
| Power consumption in sleep mode (supply current) | ICC |  | 0.05 | 2 | μA | EN=0, RS=VCC or 0V, VI=VCC | 7 |
| Power consumption in standby mode (supply current) | ICC |  | 370 | 600 | μA | EN=VCC, RS=VCC, VI=VCC | 7 |
| Dominant power consumption | ICC | 50 |  | 70 | mA | EN=VCC, VI=0V, RS=0V, LOAD=60Ω | 7 |
| Propagation delay time (low-to-high-level), driver | tPLH | 35 |  | 85 | ns | R=0, Short circuit (Fig 4) | 4 |
| Propagation delay time (low-to-high-level), driver | tPLH | 70 |  | 125 | ns | R=10kΩ | 4 |
| Propagation delay time (low-to-high-level), driver | tPLH | 500 |  | 870 | ns | R=100kΩ | 4 |
| Propagation delay time (high-to-low-level), driver | tPHL | 70 |  | 120 | ns | R=0, Short circuit (Fig 4) | 5 |
| Propagation delay time (high-to-low-level), driver | tPHL | 130 |  | 180 | ns | R=10kΩ | 5 |
| Propagation delay time (high-to-low-level), driver | tPHL | 870 |  | 1200 | ns | R=100kΩ | 5 |
| Differential output signal rise time | tr | 20 |  | 70 | ns | R=0, Short circuit (Fig 4) | 5 |
| Differential output signal rise time | tr | 30 |  | 150 | ns | R=10kΩ | 5 |
| Differential output signal rise time | tr | 350 |  | 1400 | ns | R=100kΩ | 5 |
| Differential output signal fall time | tf | 20 |  | 70 | ns | R=0, Short circuit (Fig 4) | 5 |
| Differential output signal fall time | tf | 30 |  | 150 | ns | R=10kΩ | 5 |
| Differential output signal fall time | tf | 350 |  | 1400 | ns | R=100kΩ | 5 |
| Positive-going input threshold voltage | VIT+ | 750 |  | 900 | mV | Table 1 | 5 |
| Negative-going input threshold voltage | VIT- | 500 |  | 650 | mV | Table 1 | 5 |
| Bus input current | Ii | 200 |  | 600 | μA | VIH=12V, VCC=0V | 5 |
| Bus input current | Ii | 150 |  | 500 | μA | VIH=12V, VCC=3.3V | 5 |
| Bus input current | Ii | -450 |  | -130 | μA | VIH=-7V, VCC=0V | 5 |
| Bus input current | Ii | -610 |  | -150 | μA | VIH=-7V, VCC=3.3V | 5 |
| Bus input resistance | Ri | 20 | 35 | 50 | kΩ | Corresponding standards of ISO 11898-2 | 5 |
| Propagation delay time (low-to-high-level), receiver | tPLH | 35 |  | 60 | ns | Fig 6 | 6 |
| Propagation delay time (high-to-low-level), receiver | tPHL | 35 |  | 60 | ns | Fig 6 | 6 |
| Output signal rise time, receiver | tr | 2 |  | 5 | ns | Fig 6 | 6 |
| Output signal fall time, receiver | tf | 2 |  | 5 | ns | Fig 6 | 6 |
| Differential input resistance | Rdiff | 40 |  | 100 | kΩ | Corresponding standards of ISO 11898-2 | 6 |
| Total loop delay, driver input to receiver output, recessive to dominant | t(LOOP1) | 70 |  | 135 | ns | R=0, Short circuit (Fig 9) | 6 |
| Total loop delay, driver input to receiver output, recessive to dominant | t(LOOP1) | 105 |  | 190 | ns | R=10 kΩ | 6 |
| Total loop delay, driver input to receiver output, recessive to dominant | t(LOOP1) | 535 |  | 1000 | ns | R=100 kΩ | 6 |
| Total loop delay, driver input to receiver output, dominant to recessive | t(LOOP2) | 70 |  | 165 | ns | R=0, Short circuit (Fig 9) | 6 |
| Total loop delay, driver input to receiver output, dominant to recessive | t(LOOP2) | 105 |  | 190 | ns | R=10 kΩ | 6 |
| Total loop delay, driver input to receiver output, dominant to recessive | t(LOOP2) | 535 |  | 1000 | ns | R=100 kΩ | 6 |
| Thermal shutdown temperature | Tj(sd) | 155 |  | 170 | ℃ |  | 7 |
| Wake-up time from standby mode | TWAKE | 0.55 |  | 1.5 | μs | RS adds square wave (Fig7) | 7 |
| Wake-up time from sleep mode | TWAKE | 1 |  | 5 | μs | EN adds square wave (Fig 8) | 7 |
| Input current for high-speed | IRS | -450 |  | 0 | μA | VRS<1V | 7 |
| Power-off leakage current | Ioff | -250 |  | 250 | μA | VCC=0V, VCANH=VCANL=5V | 7 |

## CAD (KiCad official)

- Symbol: `SIT65HVD234DR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `sit65hvd234dr-etched.step` / `sit65hvd234dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sit65hvd234dr.step` / `sit65hvd234dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [SIT datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588894481127391232) (18 pp, sha256 `0d4333e9b3ecb9d7`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sit65hvd234dr-datasheet.pdf)