component
SIT65HVD08DR
Public Made by Adomby adom
SIT RS-485 / RS-422 ICs, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSIT65HVD08DR
SIT · RS-485 / RS-422 ICs · SOP-8
SIT65HVD08DR from SIT, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RO | output | Receiver output. Logic-high when A−B ≥ +200 mV, logic-low when A−B ≤ −200 mV. High-impedance (tri-state) when /RE is high. VOH ≥ VCC−1.5 V at IOUT = −4 mA; VOL ≤ 0.4 V at IOUT = +4 mA. |
| 2 | /RE | input | Receiver output enable, active-low. Logic-low enables the receiver output RO; logic-high places RO in a high-impedance state. VIH ≥ 2.0 V, VIL ≤ 0.8 V, input current ±2 µA max. |
| 3 | DE | input | Driver output enable, active-high. Logic-high enables the differential driver outputs on pins A and B; logic-low places the driver in a high-impedance state. With DE=0 and /RE=high the device enters low-current shutdown (typ. 0.1-0.4 µA). |
| 4 | DI | input | Driver input. When the driver is enabled, a logic-low on DI forces A low and B high; a logic-high on DI forces A high and B low. VIH ≥ 2.0 V, VIL ≤ 0.8 V. |
| 5 | GND | power_in | Ground reference (0 V). |
| 6 | A | bidirectional | Non-inverting RS-485/RS-422 bus pin. Driver output A when DE is high; receiver input A when /RE is low. Tolerates −15 V to +15 V bus fault voltage and ±16 kV contact-discharge ESD. Receiver input impedance ≥ 96 kΩ (1/8 unit load). |
| 7 | B | bidirectional | Inverting RS-485/RS-422 bus pin. Driver output B when DE is high; receiver input B when /RE is low. Tolerates −15 V to +15 V bus fault voltage and ±16 kV contact-discharge ESD. Receiver input impedance ≥ 96 kΩ (1/8 unit load). |
| 8 | VCC | power_in | Power supply, 3.0 V to 5.5 V nominal (absolute max +7 V). Typical supply current 430-510 µA active; ≤ 10 µA in shutdown. Bypass with a 100 nF ceramic capacitor to GND close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SIT |
| Package | SOP-8 |
| Category | Interface |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
SIT65HVD08DRSIT65HVD08DRD
CAD (KiCad official)
- Symbol:
SIT65HVD08DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
sit65hvd08dr-etched.step/sit65hvd08dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sit65hvd08dr.step/sit65hvd08dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SIT datasheet (14 pp, sha256
c6dca4fc6d9f01d7, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).