component
SIT65176BDR
Public Made by Adomby adom
SIT RS-485 / RS-422 ICs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SIT65176BDR
SIT · RS-485 / RS-422 ICs · SOP-8
SIT65176BDR from SIT, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RO | output | Receiver output: when /RE is low, RO is high if A-B is at or above 200 mV and low if A-B is at or below -200 mV. |
| 2 | /RE | input | Receiver output enable: drive low to enable RO, which is high impedance when /RE is high; driving /RE high and DE low enters low-power shutdown mode. |
| 3 | DE | input | Driver output enable: drive high to enable the driver outputs, which are high impedance when DE is low; driving /RE high and DE low enters low-power shutdown mode. |
| 4 | DI | input | Driver input: with DE high, a low on DI forces the non-inverting output low and the inverting output high, and a high on DI forces the non-inverting output high and the inverting output low. |
| 5 | GND | power_in | Ground reference for the device; all voltages are referenced to ground. |
| 6 | A | bidirectional | Non-inverting receiver input and non-inverting driver output on the bus, with bus-side input voltage rated from -15 V to +15 V. |
| 7 | B | bidirectional | Inverting receiver input and inverting driver output on the bus, with bus-side input voltage rated from -15 V to +15 V. |
| 8 | VCC | power_in | Positive supply, operating from 3.0 V to 5.5 V and rated to a absolute maximum of 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SIT |
| Package | SOP-8 |
| Category | Interface |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Differential output voltage (no load) | VOD1 | 2.5 | 5.5 | V | 3 | ||
| Differential output voltage | VOD2 | 1.5 | 1.8 | V | Fig 2, RL = 54 Ω, VCC=3.3V | 3 | |
| Differential output voltage | VOD2 | 1.5 | 3 | V | Fig 2, RL = 54 Ω, VCC=5V | 3 | |
| Change in magnitude of differential output voltage | ΔVOD | 0.2 | V | Fig 2, RL = 54 Ω | 3 | ||
| Common-mode output voltage | VOC | 3 | V | Fig 2, RL = 54 Ω | 3 | ||
| Change in magnitude of common-mode output voltage | ΔVOC | 0.2 | V | Fig 2, RL = 54 Ω | 3 | ||
| High-level input voltage | VIH | 2 | V | DE, DI, /RE | 3 | ||
| Low-level input voltage | VIL | 0.8 | V | DE, DI, /RE | 3 | ||
| Logic input current | IIN1 | -2 | 2 | µA | DE, DI, /RE | 3 | |
| Short-circuit output current, short to HIGH | IOSD1 | 250 | mA | short to 0V~12V | 3 | ||
| Short-circuit output current, short to LOW | IOSD2 | -250 | mA | short to -7V~0V | 3 | ||
| Input current (A, B) | IIN2 | 125 | µA | DE = 0 V, VCC=0 or 5V, VIN = 12 V | 4 | ||
| Input current (A, B) | IIN2 | -100 | µA | DE = 0 V, VCC=0 or 5V, VIN = -7 V | 4 | ||
| Positive-going input threshold voltage | VIT+ | -10 | mV | -7V≤VCM≤12V | 4 | ||
| Negative-going input threshold voltage | VIT- | -200 | mV | -7V≤VCM≤12V | 4 | ||
| Input hysteresis voltage | Vhys | 10 | 30 | mV | -7V≤VCM≤12V | 4 | |
| LOW-level output voltage | VOL | 0.4 | V | IOUT = +2.5mA, VID = -200 mV | 4 | ||
| Three-state input leakage current | IOZR | -1 | 1 | µA | 0.4 V < VO < 2.4 V | 4 | |
| Receiver input resistance | RIN | 96 | kΩ | -7V≤VCM≤12V | 4 | ||
| Receiver output short-circuit current | IOSR | -8 | 90 | mA | 0 V≤VO≤VCC | 4 | |
| Supply current (ICC1) | ICC1 | 240 | 650 | µA | /RE=0V, DE=0V, VCC=3.3V | 5 | |
| Supply current (ICC1) | ICC1 | 270 | 750 | µA | /RE=0V, DE = 0 V, VCC=5V | 5 | |
| Supply current (ICC2) | ICC2 | 250 | 650 | µA | /RE=VCC, DE=VCC, VCC=3.3V | 5 | |
| Supply current (ICC2) | ICC2 | 280 | 750 | µA | /RE=0V, DE = 0 V, VCC=5V | 5 | |
| Shutdown current | ISHDN | 0.2 | 10 | µA | /RE=VCC, DE=0V, VCC=3.3V | 5 | |
| Differential-output delay time | tDD | 15 | 32 | ns | RDIFF = 60 Ω, CL1=CL2=100pF (Fig 3& Fig 4) | 5 | |
| Differential-output transition time | tTD | 8 | 20 | ns | 5 | ||
| Drive propagation delay from low to high | tPLH | 18 | 40 | ns | RDIFF = 27 Ω, (Fig 3& Fig 4) | 5 | |
| Drive propagation delay from high to low | tPHL | 18 | 40 | ns | 5 | ||
| /tPLH-tPHL/ skew | tPDS | 2 | 6 | ns | 5 | ||
| Output enable time to high level | tPZH | 55 | ns | RL = 110Ω, (Fig 5& Fig 6) | 5 | ||
| Output enable time to low level | tPZL | 55 | ns | 5 | |||
| Input disable time from low level | tPLZ | 85 | ns | RL = 110Ω, (Fig 5& Fig 6) | 5 | ||
| Input disable time from high level | tPHZ | 85 | ns | 5 | |||
| Output enable time to high level (shutdown) | tDSH | 20 | 100 | ns | RL = 110Ω, (Fig 5& Fig 6) | 6 | |
| Output enable time to low level (shutdown) | tDSL | 20 | 100 | ns | RL = 110Ω, (Fig 5& Fig 6) | 6 | |
| Propagation delay time, low- to high-level output | tRPLH | 40 | 70 | ns | CL=15pF (Fig 7& Fig 8) | 6 | |
| Propagation delay time, high- to low-level output | tRPHL | 40 | 70 | ns | 6 | ||
| /tRPLH − tRPHL/ skew | tRPDS | 3 | 8 | ns | 6 | ||
| Output enable time to low level | tRPZL | 15 | 40 | ns | CL=15pF (Fig 7& Fig 8) | 6 | |
| Output enable time to high level | tRPZH | 15 | 40 | ns | CL=15pF (Fig 7& Fig 8) | 6 | |
| Output disable time from low level | tPRLZ | 25 | 55 | ns | CL=15pF (Fig 7& Fig 8) | 6 | |
| Output disable time from high level | tPRHZ | 25 | 55 | ns | CL=15pF (Fig 7& Fig 8) | 6 | |
| Output enable time to high level (shutdown) | tRPSH | 150 | 500 | ns | CL=15pF (Fig 7& Fig 8) | 6 | |
| Output enable time to low level (shutdown) | tRPSL | 150 | 500 | ns | CL=15pF (Fig 7& Fig 8) | 6 | |
| Time to shutdown | tSHDN | 50 | 300 | ns | 6 | ||
| Supply voltage (working range) | VCC | 3 | 5.5 | V | 1 | ||
| Supply Voltage | VCC | 7 | V | 2 | |||
| Control Input Voltage (/RE, DE, DI) | -0.3 | V | 2 | ||||
| Input Voltage on the Bus side (A, B) | -15 | 15 | V | 2 | |||
| Receiver Output voltage (RO) | RO | -0.3 | V | 2 | |||
| Operating Temperature Range | TA | -40 | 85 | ℃ | 2 | ||
| Storage Temperature Range | Tstg | -55 | 150 | ℃ | 2 | ||
| Continuous Power Dissipation SOP8 | 470 | mW | 2 | ||||
| Thermal-shutdown threshold temperature | 140 | ℃ | 4 | ||||
| Thermal-shutdown hysteresis temperature | 20 | ℃ | 4 |
CAD (KiCad official)
- Symbol:
SIT65176BDR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
sit65176bdr-etched.step/sit65176bdr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sit65176bdr.step/sit65176bdr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SIT datasheet (17 pp, sha256
932d4aefdad37df1, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SIT65176BDR
**SIT** · RS-485 / RS-422 ICs · SOP-8
SIT65176BDR from SIT, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RO | output | Receiver output: when /RE is low, RO is high if A-B is at or above 200 mV and low if A-B is at or below -200 mV. |
| 2 | /RE | input | Receiver output enable: drive low to enable RO, which is high impedance when /RE is high; driving /RE high and DE low enters low-power shutdown mode. |
| 3 | DE | input | Driver output enable: drive high to enable the driver outputs, which are high impedance when DE is low; driving /RE high and DE low enters low-power shutdown mode. |
| 4 | DI | input | Driver input: with DE high, a low on DI forces the non-inverting output low and the inverting output high, and a high on DI forces the non-inverting output high and the inverting output low. |
| 5 | GND | power_in | Ground reference for the device; all voltages are referenced to ground. |
| 6 | A | bidirectional | Non-inverting receiver input and non-inverting driver output on the bus, with bus-side input voltage rated from -15 V to +15 V. |
| 7 | B | bidirectional | Inverting receiver input and inverting driver output on the bus, with bus-side input voltage rated from -15 V to +15 V. |
| 8 | VCC | power_in | Positive supply, operating from 3.0 V to 5.5 V and rated to a absolute maximum of 7 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SIT |
| Package | SOP-8 |
| Category | Interface |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Differential output voltage (no load) | VOD1 | 2.5 | | 5.5 | V | | 3 |
| Differential output voltage | VOD2 | 1.5 | 1.8 | | V | Fig 2, RL = 54 Ω, VCC=3.3V | 3 |
| Differential output voltage | VOD2 | 1.5 | 3 | | V | Fig 2, RL = 54 Ω, VCC=5V | 3 |
| Change in magnitude of differential output voltage | ΔVOD | | | 0.2 | V | Fig 2, RL = 54 Ω | 3 |
| Common-mode output voltage | VOC | | | 3 | V | Fig 2, RL = 54 Ω | 3 |
| Change in magnitude of common-mode output voltage | ΔVOC | | | 0.2 | V | Fig 2, RL = 54 Ω | 3 |
| High-level input voltage | VIH | 2 | | | V | DE, DI, /RE | 3 |
| Low-level input voltage | VIL | | | 0.8 | V | DE, DI, /RE | 3 |
| Logic input current | IIN1 | -2 | | 2 | µA | DE, DI, /RE | 3 |
| Short-circuit output current, short to HIGH | IOSD1 | | | 250 | mA | short to 0V~12V | 3 |
| Short-circuit output current, short to LOW | IOSD2 | -250 | | | mA | short to -7V~0V | 3 |
| Input current (A, B) | IIN2 | | | 125 | µA | DE = 0 V, VCC=0 or 5V, VIN = 12 V | 4 |
| Input current (A, B) | IIN2 | -100 | | | µA | DE = 0 V, VCC=0 or 5V, VIN = -7 V | 4 |
| Positive-going input threshold voltage | VIT+ | | | -10 | mV | -7V≤VCM≤12V | 4 |
| Negative-going input threshold voltage | VIT- | -200 | | | mV | -7V≤VCM≤12V | 4 |
| Input hysteresis voltage | Vhys | 10 | | 30 | mV | -7V≤VCM≤12V | 4 |
| LOW-level output voltage | VOL | | | 0.4 | V | IOUT = +2.5mA, VID = -200 mV | 4 |
| Three-state input leakage current | IOZR | -1 | | 1 | µA | 0.4 V < VO < 2.4 V | 4 |
| Receiver input resistance | RIN | 96 | | | kΩ | -7V≤VCM≤12V | 4 |
| Receiver output short-circuit current | IOSR | -8 | | 90 | mA | 0 V≤VO≤VCC | 4 |
| Supply current (ICC1) | ICC1 | | 240 | 650 | µA | /RE=0V, DE=0V, VCC=3.3V | 5 |
| Supply current (ICC1) | ICC1 | | 270 | 750 | µA | /RE=0V, DE = 0 V, VCC=5V | 5 |
| Supply current (ICC2) | ICC2 | | 250 | 650 | µA | /RE=VCC, DE=VCC, VCC=3.3V | 5 |
| Supply current (ICC2) | ICC2 | | 280 | 750 | µA | /RE=0V, DE = 0 V, VCC=5V | 5 |
| Shutdown current | ISHDN | | 0.2 | 10 | µA | /RE=VCC, DE=0V, VCC=3.3V | 5 |
| Differential-output delay time | tDD | 15 | | 32 | ns | RDIFF = 60 Ω, CL1=CL2=100pF (Fig 3& Fig 4) | 5 |
| Differential-output transition time | tTD | 8 | | 20 | ns | | 5 |
| Drive propagation delay from low to high | tPLH | 18 | | 40 | ns | RDIFF = 27 Ω, (Fig 3& Fig 4) | 5 |
| Drive propagation delay from high to low | tPHL | 18 | | 40 | ns | | 5 |
| /tPLH-tPHL/ skew | tPDS | 2 | | 6 | ns | | 5 |
| Output enable time to high level | tPZH | | | 55 | ns | RL = 110Ω, (Fig 5& Fig 6) | 5 |
| Output enable time to low level | tPZL | | | 55 | ns | | 5 |
| Input disable time from low level | tPLZ | | | 85 | ns | RL = 110Ω, (Fig 5& Fig 6) | 5 |
| Input disable time from high level | tPHZ | | | 85 | ns | | 5 |
| Output enable time to high level (shutdown) | tDSH | 20 | | 100 | ns | RL = 110Ω, (Fig 5& Fig 6) | 6 |
| Output enable time to low level (shutdown) | tDSL | 20 | | 100 | ns | RL = 110Ω, (Fig 5& Fig 6) | 6 |
| Propagation delay time, low- to high-level output | tRPLH | 40 | | 70 | ns | CL=15pF (Fig 7& Fig 8) | 6 |
| Propagation delay time, high- to low-level output | tRPHL | 40 | | 70 | ns | | 6 |
| /tRPLH − tRPHL/ skew | tRPDS | 3 | | 8 | ns | | 6 |
| Output enable time to low level | tRPZL | 15 | | 40 | ns | CL=15pF (Fig 7& Fig 8) | 6 |
| Output enable time to high level | tRPZH | 15 | | 40 | ns | CL=15pF (Fig 7& Fig 8) | 6 |
| Output disable time from low level | tPRLZ | 25 | | 55 | ns | CL=15pF (Fig 7& Fig 8) | 6 |
| Output disable time from high level | tPRHZ | 25 | | 55 | ns | CL=15pF (Fig 7& Fig 8) | 6 |
| Output enable time to high level (shutdown) | tRPSH | 150 | | 500 | ns | CL=15pF (Fig 7& Fig 8) | 6 |
| Output enable time to low level (shutdown) | tRPSL | 150 | | 500 | ns | CL=15pF (Fig 7& Fig 8) | 6 |
| Time to shutdown | tSHDN | 50 | | 300 | ns | | 6 |
| Supply voltage (working range) | VCC | 3 | | 5.5 | V | | 1 |
| Supply Voltage | VCC | | | 7 | V | | 2 |
| Control Input Voltage (/RE, DE, DI) | | -0.3 | | | V | | 2 |
| Input Voltage on the Bus side (A, B) | | -15 | | 15 | V | | 2 |
| Receiver Output voltage (RO) | RO | -0.3 | | | V | | 2 |
| Operating Temperature Range | TA | -40 | | 85 | ℃ | | 2 |
| Storage Temperature Range | Tstg | -55 | | 150 | ℃ | | 2 |
| Continuous Power Dissipation SOP8 | | | | 470 | mW | | 2 |
| Thermal-shutdown threshold temperature | | | 140 | | ℃ | | 4 |
| Thermal-shutdown hysteresis temperature | | | 20 | | ℃ | | 4 |
## CAD (KiCad official)
- Symbol: `SIT65176BDR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `sit65176bdr-etched.step` / `sit65176bdr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sit65176bdr.step` / `sit65176bdr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [SIT datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884395948589056) (17 pp, sha256 `932d4aefdad37df1`, retrieved 2026-10-16, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sit65176bdr-datasheet.pdf)